BUK112-50GL Datasheet, PDF (8/16 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.6. Normalised limiting power dissipation.
P_D% = 100⋅P_D/P_D(25˚C) = f(T_mb)
ID / A
14
BUK112-50GL
12
10
8
6
4
2
0
0
50
100
150
Tmb / C
Fig.7. Continuous limiting drain current.
I_D = f(T_mb); conditions: V_IS = 5 V; V_PS = 5 V
ID / A
25
WITH PROTECTION
20
15
CURRENT LIMITING
10
5
BUK112-50GL
VIS / V =
7
6
5
4
3
0
0
5
10
15
20
25
30
VDS / V
Fig.8. Typical output characteristics, T_j = 25˚C.
I_D = f(V_DS); t_p = 250 µs; V_PS = 5 V; parameter V_IS
Product specification
BUK112-50GL
ID / A
50
WITHOUT PROTECTION
40
30
20
10
BUK112-50GL
VIS / V = ₇
6
5
4
3
0
0
5
10
15
20
VDS / V
Fig.9. Typical output characteristics, T_j = 25˚C.
I_D = f(V_DS); t_p = 250 µs; V_PS = 0 V; parameter V_IS
ID / A
30
25
WITHOUT PROTECTION
BUK112-50GL
VPS = 0 V
20
VPS = 5 V
15
CURRENT LIMITING
10
WITH PROTECTION
5
0
0
1
2
3
4
5
VDS / V
Fig.10. Typical on-state characteristics, T_j = 25˚C.
I_D = f(V_DS); V_IS = 5 V; t_p = 250 µs; parameter V_PS
RDS(ON) / mOhm
200
BUK112-50GL
150
TYP.
100
50
0
0
1
2
3
4
5
6
7
8
VIS / V
Fig.11. Typical on-state resistance, T_j = 25˚C.
R_DS(ON) = f(V_IS); t_p = 250 µs; parameter V_IS
September 1996
8
Rev 1.000