BUK112-50GL Datasheet, PDF (12/16 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
ID / A
12
BUK112-50GL
10
8
6
4
2
0
50
55
60
65
70
VIS / V
Fig.30. Typical clamping characteristics, 25˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 50 µs
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.31. Normalised limiting clamping energy.
E_DSM% = f(T_mb); conditions: I_D = 6 A
VDS
0
ID
0
VIS
0
V(CL)DSP
VDD
L
+ ^VDD
+ ^VPS
VDS
-
RF
D
TOPFET
P
P
F
I
D.U.T.
R 01
S
shunt
-ID/100
Fig.32. Clamping energy test circuit.
E_DSM = 0.5 ⋅ L I_D² ⋅ V_(CL)DSS/(V_(CL)DSS − V_DD)
Product specification
BUK112-50GL
5 ^{ID / mA}
4
BUK112-50GL
OVERVOLTAGE CLAMPING
3
OPEN CIRCUIT LOAD DETECTION
2
VPS = 5 V
IDSP
1
IDSF
VPS = 0 V
IDSS
0
0
10
20
30
40
50
60
70
VDS / V
Fig.33. Typical off-state characteristics, T_j = 25˚C.
I_D = f(V_DS); V_IS = 0 V; parameter V_PS
IDSP & IDSF / mA
2
1.5
1
IDSP
BUK112-50GL
IDSF
0.5
0
0
2
4
6
8
VPS / V
Fig.34. Typical open circuit load detect currents.
I_DSP & I_DSF = f(V_PS); V_IS = 0 V; V_DS ≥ 5 V; T_j = 25˚C
IDSP & IDSF / mA
2
BUK112-50GL
1.5
IDSP
1
IDSF
0.5
0
-50
0
50
100
150
200
Tmb / C
Fig.35. Typical open circuit load detect currents.
I_DSP & I_DSF = f(T_j); V_PS = 5 V; V_IS = 0 V
September 1996
12
Rev 1.000