BUK112-50GL Datasheet, PDF (10/16 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
II / mA
2
BUK112-50GL
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
VIS / V
Fig.18. Typical DC input characteristic.
I_I = f(V_IS) normal operation; T_j = 25˚C
IISL / mA
8
BUK112-50GL
7
6
5
4
3
2
1
00
1
2
3
4
5
6
7
8
VIS / V
Fig.19. Typical DC input characteristic, T_j = 25˚C.
I_ISL = f(V_IS) overload protection latched; V_PS = 5 V
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.20. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
Product specification
BUK112-50GL
IP / mA
2
BUK112-50GL
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
VPS / V
Fig.21. Typical protection supply characteristics.
I_P = f(V_PS); normal or overload operation; T_j = 25˚C
IF / mA
2
BUK112-50GL
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
VFS / V
Fig.22. Typical flag high characteristic, T_j = 25˚C.
I_F = f(V_FS); refer to TRUTH TABLE
IF / uA
200
BUK112-50GL
150
100
50
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VFS / F
Fig.23. Typical flag low characteristic, T_j = 25˚C.
I_F = f(V_FS); V_PS = 5 V; refer to TRUTH TABLE
September 1996
10
Rev 1.000