BUK112-50GL Datasheet, PDF (13/16 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK112-50GL
Idss
1 mA
100 uA
10 uA
typ.
1 uA
100 nA
0
20
40
60
80 100 120 140
Tj / C
Fig.36. Typical off-state leakage current.
I_DSS = f(T_j); Conditions: V_DS = 40 V; V_IS = 0 V.
ID & IDM / A
100
RDS(ON) ^{= VDS/ID}
BUK112-50GL
tp =
10 us
100 us
10
DC
1 ms
Overload protection
characteristics not shown.
1
1
10
VDS / V
10 ms
100 ms
100
Fig.37. Safe operating area, V_PS = 0 V, T_mb = 25˚C.
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth / (K/W)
10
BUK112-50GL
D=
1
0.5
0.2
0.1
0.05
0.1
0.02
P_D
tp
D=
tp
T
0
0.01
1E-07
1E-05
1E-03
t/s
T
t
1E-01
1E+01
Fig.38. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
Coss
10 nF
BUK112-50GL
1 nF
100 pF
0
10
20
30
40
50
VDS / V
Fig.39. Typical output capacitance.
C_oss = f(V_DS); conditions: V_IS = 0 V; f = 1 MHz
September 1996
13
Rev 1.000