TDA4841PS Datasheet, PDF (40/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4841PS
handbook, full pagewidth
(ANY Mode)
VCC < 8.1 V
Power-Down Mode
no acknowledge is given by IC
all register contents are random
L1 ⁽¹⁾
MGM079
VCC
8.6 V
8.1 V
VCC
8.6 V
8.1 V
a soft-down sequency followed by a
soft start sequence is generated
internally.
IC enters standby mode.
(1) See Fig.18.
Fig.20 I²C-bus flow for any mode.
Power-down mode
Power dip of V_CC < 8.6 V:
• The soft-down sequence is started first
• Then the soft-start sequence is generated internally.
Power dip of V_CC < 8.1 V or V_CC shut-down:
• This function is independent from the operating mode,
therefore it works under any condition
• All driver outputs are immediately disabled
• IC enters standby mode.
Standby mode detection
Execute data transmission twice to assure that there was
no data transfer error.
Normal operation
I²C-bus transmission
chip address
subaddress
S
8CH
A
0XH
A
data
XXH
AP
yes
acknowledge was
given on data?
no
I²C-bus transmission
chip address
subaddress
S
8CH
A
0XH
A
data
XXH
AP
1999 Oct 25
yes
acknowledge was
given on data?
no
Standby mode
MGS276
Fig.21 Possible standby mode detection.
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