TDA4841PS Datasheet, PDF (38/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4841PS
START
Power-down mode (XXXX XXXX)
L1
no acknowledge is given by IC
all register contents are random
VCC > 8.3 V
Standby mode (XXXX XX01)
L2
STDBY = 1
SOFTST = 0
all other register contents are random
S 8CH A 1AH A 00H A P
Protection mode (XXXX XX00)
STDBY = 0
SOFTST = 0
all other register contents are random
S 8CH A SAD A DATA A P
Protection mode (XXXX XX00)
STDBY = 0
SOFTST = 0
registers are pre-set
no _{all registers defined?}
yes
S 8CH A 1AH A 02H A P
L3
Soft-start sequence (XXXX XX10)
STDBY = 0
SOFTST = 1
Operating mode (XXXX XX10)
STDBY = 0
SOFTST = 1
no
change/refresh of data?
yes
S 8CH A SAD A DATA A P
no
SOFTST = 0?
yes
L4 ⁽¹⁾
MGL791
(1) See Fig.19.
Fig.18 I²C-bus flow for start-up.
Start-up procedure
V_CC < 8.3 V:
• As long as the supply voltage is too low for correct
operation, the IC will give no acknowledge due to
internal Power-On Reset (POR)
• Supply current is 9 mA or less.
V_CC > 8.3 V:
• Internal POR has ended and the IC is in standby mode
• Control bits STDBY and SOFTST are reset to their start
values
• All other register contents are random
• Pin HUNLOCK is at HIGH-level.
Setting control bit STDBY = 0:
• Enables internal power supply
• Supply current increases from 9 to 70 mA
• When V_CC < 8.6 V register SOFTST cannot be set by
the I²C-bus
• Output stages are disabled
• Pin HUNLOCK is at HIGH-level.
Setting all registers to defined values:
• Due to the hardware configuration of the IC
(no auto-increment) any register setting needs a
complete 3-byte I²C-bus data transfer as follows:
START - IC address - subaddress - data - STOP.
Setting control bit SOFTST = 1:
• Before enabling the soft-start sequence a delay of
minimum 80 ms is necessary to obtain correct function
of the horizontal drive
• HDRV duty cycle increases
• BDRV duty cycle increases
• VOUT1 and VOUT2 are enabled
• PLL1 and PLL2 are enabled.
IC in full operation:
• Pin HUNLOCK is at LOW-level when PLL1 is locked
• Any change of the register content will result in an
immediate change of the output behaviour
• Setting control bit SOFTST = 0 is the only way (except
power-down via pin V_CC) to leave the operating mode.
Soft-down sequence:
• See L4 of Fig.19 for starting the soft-down sequence.
1999 Oct 25
38