TDA4841PS Datasheet, PDF (4/60 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

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VSYNC 14
(TTL level)
VERTICAL
SYNC INPUT
AND POLARITY
CORRECTION
clamping
blanking
CLBL 16
VIDEO CLAMPING
AND
VERTICAL BLANK
HUNLOCK
17 _HUNLOCK
OUTPUT
SDA
SCL
VCC
9.2 to 16 V
19
I²C-BUS
18 _RECEIVER
10
PGND 7
SGND 25
SUPPLY
AND
REFERENCE
22
kΩ
(1%)
100
nF
(5%)
EHT compensation
via vertical size
EHT compensation
150
via horizontal size
nF
VREF
23
VCAP VAGC
24
22
VSMOD
21
HSMOD
31
EWDRV
11
7V
1.2 V
VERTICAL
SYNC
INTEGRATOR
VERTICAL
OSCILLATOR
AND AGC
EHT COMPENSATION
HORIZONTAL SIZE
AND
VERTICAL SIZE
EW-OUTPUT
HORIZONTAL PINCUSHION
HORIZONTAL CORNER
HORIZONTAL TRAPEZIUM
HORIZONTAL SIZE
VERTICAL OUTPUT ¹²
VERTICAL LINEARITY
VERTICAL LINEARITY ¹³
BALANCE
VOUT2
VOUT1
VERTICAL POSITION
VERTICAL SIZE, VOVSCN
PROTECTION
AND SOFT START
I²C-BUS REGISTERS
COINCIDENCE DETECTOR
FREQUENCY DETECTOR
TDA4841PS
X-RAY
PROTECTION
OUTPUT
20 ASCOR
or
ASYMMETRIC
EW-CORRECTION
FOCUS
HORIZONTAL
AND VERTICAL
B+
CONTROL
32 FOCUS
6 BDRV
4 BSENS
3 BOP
5 BIN
X-RAY
B+ CONTROL(2)
APPLICATION
HSYNC 15
(TTL level)
H/C SYNC INPUT
AND POLARITY
CORRECTION
(video)
PLL1 AND
HORIZONTAL
POSITION
HORIZONTAL
OSCILLATOR
3.3 kΩ
100 nF
26
27
HPLL1 HBUF
28
HREF
8.2
RHBUF ₍₁₎
nF
RHREF
(1%)
29
HCAP
10 nF
(2%)
PLL2, PARALLELOGRAM,
PIN UNBALANCE AND
SOFT START
30
HPLL2
12 nF
1
HFLB
9
2
XSEL XRAY
HORIZONTAL
OUTPUT
STAGE
8 HDRV
MHB603
(1) For the calculation of f_H range see Section “Calculation of line frequency range”.
(2) See Figs 25 and 26.
Fig.1 Block diagram and application circuit.