SAA7712H Datasheet, PDF (35/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
16 I²C-BUS TIMING CHARACTERISTICS
Timing of the I²C-bus (see Fig.18); all values referred to V_IH and V_IL (see Section 12).
SYMBOL
PARAMETER
CONDITIONS
MIN.
f_SCL
t_BUF
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_r
t_f
t_SU;STO
C_b
t_SP
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START
condition; after this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
data hold time
data set-up time
rise time of both SDA and SCL
signals
fall time of both SDA and SCL
signals
set-up time for STOP condition
capacitive load for each bus line
maximum pulse width for spike
suppression
for standard mode I²C-bus
system t_SU;DAT > 250 ns
f_SCL = 400 kHz
f_SCL = 100 kHz
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C_b(1)
20 + 0.1C_b(1)
20 + 0.1C_b(1)
0.6
−
−
MAX.
400
−
−
−
−
−
0.9
−
300
1 000
300
−
400
50
Note
1. C_b is the bus line capacitance in pF.
UNIT
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
ns
1999 Aug 05
35