SAA7712H Datasheet, PDF (17/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
Table 4 I²C-bus host_io_format bits (0FF9H, see Table 13)
HOST_IO_FORMAT
BIT 11
0
0
1
1
BIT 10
0
1
0
1
Table 5 I²C-bus cloop_mode bits (0FF9H, see Table 13)
CLOOP_MODE
BIT 15
0
1
−
−
−
−
BIT 14
−
−
0
0
1
1
BIT 13
−
−
0
1
0
1
OUTPUT
standard I²S-bus (default)
LSB-justified format, 16 bits
LSB-justified format, 18 bits
LSB-justified format, 20 bits
OUTPUT
bypass WS (default)
WS 50% duty factor
bypass BCLK (default)
divide BCLK by 2
divide BCLK by 4
divide BCLK by 8
8.3 Equalizer accelerator
8.3.1 INTRODUCTION
The equalizer accelerator is a hardware accelerator to the
DSP core. Both its inputs and outputs are stored in
registers of the DSP core.
The equalizer cannot be used and cannot be programmed
if no word select and bit clock signal are present on a
selected digital source input; see audio_source bit in
Table 3 (I²S_IN1 or I²S_IN2). The minimum required
DSP_clock is 481f_s.
The equalizer accelerator contains one second-order filter
data path that is 20 times multiplexed. With this circuit, a
2-channel equalizer of 10 second-order sections per
channel or a 4-channel equalizer of 5 second-order
sections per channel can be realised. The centre
frequency, gain and Q-factor of all 20 second-order
sections can be set independently from each other. Every
section is followed by a selectable attenuation of 0 or 6 dB.
Per section, 4 bytes of the I²C-bus register are needed to
store the settings. The equalizer settings can be updated
during normal operation. An application program supports
the programming of the equalizer.
If the gain setting causes the audio signal to exceed the
maximum level in one of the filter sections, the signal will
be clipped and the equalizer overflow output (pin EQOV)
will be set HIGH until the end of the next audio sample
period.
8.3.2 CONFIGURATION OF EQUALIZER SECTIONS
The equalizer accelerator can make a 2-channel equalizer
of 10 second-order sections per channel or a 4-channel
equalizer of 5 second-order sections per channel.
The sections of one channel can be chained one after the
other. Depending on the I²C-bus control bit two_four
(see Table 11), the 20 filter sections are combined for the
appropriate configuration, as illustrated in Fig.8.
1999 Aug 05
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