SAA7712H Datasheet, PDF (16/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.2.2 SLAVE I²S-BUS INPUTS
The SAA7712H has two slave I²S-bus inputs, I²S_IN1 and
I²S_IN2 with respective data lines I²S_IN1_DATA and
I²S_IN2_DATA, word select lines I²S_IN1_WS and
I²S_IN2_WS and bit clock lines I²S_IN1_BCK and
I²S_IN2_BCK. The external source is master and supplies
the bit clock and word select. The I²C-bus bits
audio_format(2 to 0) allow for selection of the desired
I²S-bus format (see Table 13). The bits, needed for
selecting a certain format, are explained in Table 2.
The input circuitry is limited in handling the number of BCK
pulses per WS period. If the word rate of the selected
digital input source is f_s, the bit clock must be a continuous
clock in the range of 16f_s ≤ f_bit(CLK) ≤ 256f_s. The minimum
limit of the audio sample frequency is determined by
1_{⁄18fSCL. The maximum limit of the audio sample frequency}
is determined by DSP_clock/481 Hz.
Table 2 I²C-bus audio_format mode bits (0FF9H,
see Table 13)
AUDIO_FORMAT
BIT 9 BIT 8 BIT 7
OUTPUT
0
0
0 internal format (for test
purposes only)
−
0
1 LSB-justified, 16 bits
−
1
0 LSB-justified, 18 bits
−
1
1 LSB-justified, 20 bits
1
0
0 standard I²S-bus (default)
Table 3 I²C-bus audio_source mode bit (0FF9H,
see Table 13)
AUDIO_SOURCE
Bit 5
0
1
OUTPUT
I²S_IN1 (default)
I²S_IN2
8.2.3 MASTER I²S-BUS INPUTS AND OUTPUTS
For the co-processor I/O interface, the SAA7712H acts as
a master. The SAA7712H supplies both the bit clock and
word select. The I²C-bus bits host_io_format(1 and 0)
allow for selection of the desired I²S-bus format (see
Table 13).
The bits needed for selecting a certain format are given in
Table 4.
All I²S-bus output lines, I²S_IO_WS, I²S_IO_BCK,
I²S_IO_OUT1 and I²S_IO_OUT2, can be 3-stated with
I²C-bus bit en_host_io (see Table 13).
The word select and bit clock of the co-processor I/O
interface are derived from the word select and bit clock of
the audio source selected according to Table 3.
The incoming bit clock can be divided by 1, 2, 4 or 8
depending on the needs of an external connected
co-processor. These selections can be done with I²C-bus
bits cloop_mode(2 to 0) (see Table 13). The meaning of
these bits is shown in Table 5.
The selection of the DSP input among the decimated
analog input and the I²S-bus inputs I²S_IN1 and I²S_IN2
is controlled with I²C-bus bit audio_source (see Table 13).
The meaning of this bit can be found in Table 3.
1999 Aug 05
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