SAA7712H Datasheet, PDF (20/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.5 Programmable phase-locked loop circuit
The clock of the DSP is generated with a programmable PLL.
To select the required DSP clock see Table 6. The N factor (ranging from 93 to 181) can be selected with I²C-bus bits
PLL_div(14 to 11), see Table 10. Depending on the crystal and the required DSP clock the I²C-bus bits pll_fs_sel and
bits dsp_turbo must be set. The maximum limit of the audio sample frequency is determined by DSP_clock/481 Hz.
Table 6 I²C-bus bits PLL_div and dividing factors N of the programmable DSP clock
PLL_DIV(14 to 11)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
N
93 (default)
99
106
113
121
126
132
137
143
148
154
159
165
170
176
181
DSP CLOCK FREQUENCY (MHz)
TDA9875⁽¹⁾
MSP3410D⁽²⁾
23.808⁽³⁾
25.344⁽³⁾
27.136
28.928
30.976
32.256
33.792⁽³⁾
35.072⁽³⁾
36.608⁽³⁾
37.888⁽³⁾
39.424⁽³⁾
40.704⁽³⁾
42.240⁽³⁾
43.520⁽³⁾
45.056⁽³⁾
46.336⁽³⁾
26.784
28.512
30.528
32.544
34.848⁽³⁾
36.288⁽³⁾
38.016⁽³⁾
39.456⁽³⁾
41.184⁽³⁾
42.624⁽³⁾
44.352⁽³⁾
45.792⁽³⁾
47.520⁽³⁾
48.960⁽³⁾
50.688⁽³⁾
52.128⁽³⁾
Notes
1. f_xtal = 16.384 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
2. f_xtal = 18.432 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
3. Usable frequency.
1999 Aug 05
20