SAA7712H Datasheet, PDF (14/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.1.8 PIN VREFDA
With two internal resistors half the supply voltage (V_DDA2)
is obtained and coupled to an internal buffer. This
reference voltage is used as DC voltage for the output
operational amplifiers and as reference for the DAC.
In order to obtain the lowest noise and to have the best
ripple rejection, a filter capacitor has to be added between
this pin and ground.
8.1.9 INTERNAL DAC CURRENT REFERENCE
As a reference for the internal DAC current and for the
DAC current source output, a current is drawn from the
level on pin VREFDA to pin V_SSA2 (ground) via an internal
resistor. The absolute value of this resistor also
determines the absolute current of the DAC. This means
that the absolute value of the current is not that fixed due
to the spread of the current reference resistor value. This,
however, does not influence the absolute output voltages
because these voltages are also derived from a
conversion of the DAC current to the actual output voltage
via internal resistors.
8.1.10 SUPPLY OF THE ANALOG OUTPUTS
All the analog circuitry of the DACs and the operational
amplifiers are fed by 2 supply pins, V_DDA2 and V_SSA2.
Pin V_DDA2 must have sufficient decoupling to prevent THD
degradation and to ensure a good power supply rejection
ratio.
The digital part of the DAC is fully supplied from the chip
core supply.
8.2 I²S-bus inputs and outputs
8.2.1 DIGITAL DATA STREAM FORMATS
For communication with external digital sources a serial
3-line bus is used. This I²S-bus has one line for data, one
line for clock and one line for the word select.
See Fig.7 for the general waveform formats of the four
possible formats.
The serial digital inputs (and outputs) of the SAA7712H are
capable of handling multiple formats: Philips I²S-bus and
LSB-justified formats of 16, 18 and 20 bits word sizes.
In Philips I²S-bus format, the number of bit clock (BCK)
pulses may vary in the application. When the transmitter
word length is smaller than the receiver word length, the
receiver will fill in zeroes at the LSB side. When the
transmitter word length exceeds the receiver word length,
the LSBs are skipped. For correct operation of the DACs,
there should be a minimum of 16 bit clocks per word
select.
In the LSB-justified formats, the transmitter and receiver
must be set to the same format. Be aware that a format
switch between 20, 18 and 16 bits LSB-justified formats is
done by changing the relative timing of the word select
edges. The data bits remain unchanged. In the 20 bits
format, the 2 LSBs are zeroes. In the 16 bits format, the
2 data bits following the word select edge are not zero, but
undefined. In fact, these are the LSBs of the 18-bit word.
The timing specification for the waveforms of the serial
digital inputs and outputs are given in Fig.17.
1999 Aug 05
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