SAA7712H Datasheet, PDF (21/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.6 I²C-bus control
8.6.1 INTRODUCTION
A general description of the I²C-bus format can be
obtained from Philips Semiconductors, International
Marketing and Sales Communications (IMSC).
For the external control of the SAA7712H a fast I²C-bus
is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are different types of control instructions:
• Instructions to control the DSP program, program the
coefficient RAM and read the values of parameters
• Instructions to control the equalizer, program the
equalizer coefficient RAM to be able to change the
centre frequency, gain and Q-factor of the equalizer
sections
• Instructions to control the source selection and
programmable parts, e.g. PLL clock speed.
The detailed description of the I²C-bus and commands is
given in the following sections. The description of the
different bits in the memory map is given in Section 9.6.
The equalizer cannot be used and cannot be
programmed if there is no word select and bit clock signal
present on a selected digital source input; see
audio_source bit in Table 3 (I²S_IN1 and I²S_IN2).
The minimum limit of the audio sample frequency is
determined by ¹â„₁₈f_SCL.
8.6.2 CHARACTERISTICS OF THE I²C-BUS
The I²C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must
be connected to V_DD via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz I²C-bus the recommendation from Philips
Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 to 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
8.6.3 BIT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals
(see Fig.11). The maximum clock frequency is 400 kHz.
To be able to run on this high frequency all the inputs and
outputs connected to this bus must be designed for this
high speed I²C-bus according to the Philips specification.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MGS216
Fig.11 Bit transfer on the I²C-bus.
1999 Aug 05
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