SAA7712H Datasheet, PDF (23/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.6.6 ACKNOWLEDGE
The number of data bits transferred between the START
and STOP conditions from the transmitter to the receiver
is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.13). The acknowledge bit is a
HIGH-level left on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line (left HIGH by the transmitter) during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.14).
8.6.7
STATE OF THE I²C-BUS INTERFACE DURING AND
AFTER POWER-ON RESET
During reset (see Section 8.8), the internal SDA line is kept
HIGH and pin SDA is therefore high-impedance. The SDA
line remains HIGH until a master pulls it down to initiate
communication.
handbook, full pagewidth
data output
by transmitter
data output
by receiver
SCL from
master
1
2
S
START condition
not acknowledge
acknowledge
7
8
9
MGS219
clock pulse for
acknowledgement
Fig.14 Acknowledge on the I²C-bus.
1999 Aug 05
23