SAA7712H Datasheet, PDF (24/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.7 External control pins
For external control two input pins are implemented.
The status of these pins can be changed by applying a
logic level. The status of these pins is recorded in the
internal status register. The function of each input pin is
determined by the DSP software.
Pin DSP_IN1:
• Logic 0 or left open-circuit means volume coefficients
updates are possible (default)
• Logic 1 means no updates of volume coefficients are
possible.
Pin DSP_IN2:
• If the 3-band spectrum analyser is used:
– Logic 1 will reset the band registers of the analyser
– Logic 0 or left open-circuit means no reset of the
band registers will be done (default).
• If the 3-band spectrum analyser is not used:
– The state of pin DSP_IN2 can be read via an I²C-bus
command.
To control external devices two output pins are
implemented. The status of these pins is controlled by the
DSP program. The functions of these pins are determined
by the DSP software.
Pin DSP_OUT1:
• To drive pin DSP_OUT1 via an I²C-bus command.
Pin DSP_OUT2:
• To drive pin DSP_OUT2 via an I²C-bus command.
A more or less fixed relationship between the
DSP_RESET time constant and the POM time constant is
obligatory. The voltage on pin POM determines the current
flowing in the DACs. For 0 V on pin POM, the DAC
currents are zero and so also the DACs output voltages.
When a 3 V supply voltage (V_DDA2) is supplied to pin POM,
the DAC currents are at their nominal (maximum) value.
Long before the DAC outputs get their nominal output
voltages, the DSP must be in normal operating mode to
reset the output register. Therefore, the time constant of
DSP_RESET must be shorter than the time constant of
POM. For advised capacitors see the application diagram.
The reset has the following function:
• All I²C-bus registers are reset to their default values
• The DSP algorithm is re-started
• The external control output pins are reset
(see Section 8.7)
• Pin SDA is high-impedance.
When the level on the reset pin is HIGH, the DSP algorithm
starts to run.
In addition to the reset pin, there is also a software reset;
bit PC_reset (bit 15, 0FFDH, see Table 11). This reset has
the following function:
• The DSP algorithm is re-started
• The external control output pins are reset
(see Section 8.7).
8.8 Reset pin
The reset signal on pin DSP_RESET is active LOW and
has an internal pull-up resistor. Between this pin and
ground a capacitor should be connected to allow a proper
switch-on of the supply voltage. The capacitor value is
such that the chip is in the reset state as long as the power
supply is not stabilized.
1999 Aug 05
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