SAA7712H Datasheet, PDF (25/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
8.9 Power supply connection and EMC
The digital part of the chip has in total 5 positive supply line
connections and 8 ground connections. To minimise
radiation the chip should be put on a double layer PCB with
a large ground plane on one side. The ground supply lines
should have a short connection to this ground plane. A coil
and capacitor network in the positive supply line can be
used as high frequency filter.
8.10 Test mode connections
Pins TSCAN, RTCB and SHTCB are used to put the chip
in test mode and to test the internal connections. Each pin
has an internal pull-down resistor to ground. In the
application these pins can be left open-circuit or connected
to ground.
9.3 Write cycles
The I²C-bus configuration for a write cycle is shown in
Fig.15. The write cycle is used to write the bytes to control
the PLL for the DSP clock generation, the format of the
I²S-bus and some other settings. More details can be
found in the I²C-bus memory map (see Table 8).
The data length is 2 or 3 bytes, depending on the
accessed memory. The slave receiver detects the address
and adjusts the number of bytes accordingly. For XRAM,
the data word length is 18 bits and 3 bytes are sent over
the I²C-bus. The upper 6 bits (i.e. bit 7 to bit 2) of the first
byte DATA H are don’t care. For YRAM, the data word
length is 12 bits and 2 bytes are sent over the I²C-bus. The
left nibble (i.e. bit 7 to bit 4) of the first byte DATA H is don’t
care.
9 I²C-BUS FORMAT
9.1 Addressing
Before any data is transmitted on the I²C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.
9.2 Slave address (pin A0)
The SAA7712H acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The slave address is shown in Table 7.
Table 7 Slave address
MSB
LSB
0
0
1
1
1
1 A0 R/W
The subaddress bit A0 corresponds to the hardware
address pin A0 which allows the device to have two
addresses. This allows the control of two SAA7712Hs via
the same I²C-bus.
9.4 Read cycles
The I²C-bus configuration for a read cycle is shown in
Fig.16. The read cycle is used to read the data values from
XRAM or YRAM. The master starts with a START
condition (S), the SAA7712H address ‘0011110’ and a
logic 0 (write) for the read/write bit. This is followed by an
acknowledge of the SAA7712H. The master then writes
the memory high address and memory low address where
the reading of the memory content of the SAA7712H must
start. The SAA7712H acknowledges these addresses
both.
The master than generates a repeated START and again
the SAA7712H address ‘0011110’ but this time followed
by a logic 1 (read) of the read/write bit. From this moment
on, the SAA7712H will send the memory content in groups
of 2 (YRAM) or 3 (XRAM) bytes to the I²C-bus, each time
acknowledged by the master. The master stops this cycle
by generating a negative acknowledge, then the
SAA7712H frees the I²C-bus and the master can generate
a STOP condition (P).
1999 Aug 05
25