SAA7712H Datasheet, PDF (27/44 Pages) NXP Semiconductors – Sound effects DSP

Philips Semiconductors
Sound effects DSP
Preliminary specification
SAA7712H
9.5 I²C-bus memory map summary
The I²C-bus memory map contains all defined I²C-bus bits. The map is split into two different sections: hardware memory
registers and the RAM definitions. The preliminary memory map is given in Table 8.
Table 8 I²C-bus memory map
SUBADDRESSES
0FF9H to 0FFFH
0F80H to 0FA7H
0800H to 097FH
0000H to 017FH
FUNCTION
various settings (see Table 9)
equalizer
YRAM
XRAM
SIZE
4 × 16 bits
40 × 16 bits
384 × 12 bits
384 × 18 bits
Table 9 I²C-bus memory map: overview of various settings
I²C_DCS_CTR
I²C_ADDA
I²C_SEL
I²C_HOST
REGISTER NAME
SUBADDRESS
0FFFH (see Table 10)
0FFDH (see Table 11)
0FFAH (see Table 12)
0FF9H (see Table 13)
9.6 I²C-bus memory map details
Table 10 I²C_DCS_CTR register (0FFFH)
NAME
−
loopo_on_off
PLL_div
−
SIZE
(BITS)
DESCRIPTION
DEFAULT
10 reserved
1 pin SYS_CLK output enable: on (logic 1) or off (logic 0) off
4 PLL clock division factor for DSP_clock (see Table 6) 93
1 reserved
BIT POSITION
9 to 0
10
14 to 11
15
1999 Aug 05
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