SA2400A Datasheet, PDF (24/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
14.4.2 Programming Example
Program synthesizer for 2.412 GHz band
• Input Xtal is 44 MHz, comparison frequency f_comp = 4 MHz ⇒
reference division ratio R = 11
• Target frequency is 2412 MHz, f_comp = 4 MHz ⇒ main divider ratio
N = 603 (no fractional N)
– write this word to register 00: 00 0 000 0000001001011011 00
(note two leading zeros – unused bits 22, 23)
– write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx
(x = no significance)
Program synthesizer for 2.462 GHz band
• Input Xtal is 44 MHz, comparison frequency f_comp = 4 MHz ⇒
reference division ratio R = 11
• Target frequency is 2462 MHz, f_comp = 4 MHz ⇒ main divider ratio
N = 615.5 (fractional 4/8)
– write this word to register 00: 00 0 100 0000001001100111 00
– write this word to register 01: 00 0000001011 00 1 0 01010000
Fractional compensation setting should be set in the application
(depends on the loop parameters) with the help of the SA8027
application note. The nominal value is FC = 640 / FM
(FM = modulus, see address 00).
14.5 Fast serial interface for Receiver–AGC
programming
When the chip is in mode “FASTTXRXMGC” the internal AGC block
is disabled. Instead, the 10 bits controlling the receiver gain and the
two bits controlling the DC offset cancellation corner frequency can be
programmed directly via a dedicated second serial interface. This
interface is active when in FASTTXRXMGC mode and when
SEN=HIGH. (SEN acts as a switch between the regular serial
interface and the dedicated bus).
14.5.1 Description of “fast programming” cycle
1. Set the chip to FASTTXRXMGC mode by programming
register 4 with the correct value.
2. Set the SEN pin to HIGH.
3. With each rising edge on pin SCLK, a new data bit is expected at
pin AGCRESET. No address is needed. The sequence of the
bits is the same as described for register 6, bits 0–11. The
programming order is LSB first.
4. With the 12^th rising edge on SCLK, an internal counter will
automatically parallel-load the shifted-in data bits into an internal
register. The bits will immediately effect the receiver settings.
5. The regular 3-wire bus is still accessible and can be
programmed when SEN is LOW. Clock activity on SCLK will not
affect receiver gain settings when SEN is LOW.
SCLK
SEN
SDATA
AGCRESET
T_cyc
t_r
t_f
1
2
31
32
1
2
3
4
5
11
12
1
A0
A1
D23
D23
XX
A0
D0
D1
D2
D3
D4
D10
D11
XX
T_on
T_setup
T_hold
3–WIRE BUS PROGRAMMING
“FAST BUS” PROGRAMMING
Figure 11. “Fast programming” cycle timing diagram
SR02311
14.6 Fast serial interface AC characteristics
SYMBOL
PARAMETER
Serial Bus Logic Level Requirements
V_IH
HIGH logic input voltage
V_IL
LOW logic input voltage
Serial Programming Clock, SCLK
t_r
Input rise time
t_f
Input fall time
T_cyc
Clock period
Enable Programming, SEN
T_on
Delay to rising clock edge
Data Programming, AGCRESET
T_setup
T_hold
Input data to clock set-up time
Input data to clock hold time
TEST CONDITIONS
LIMITS
UNITS
Min
Typ
Max
0.5×V_DD
–
–0.3
–
–
10
–
10
22
100
V_DD + 0.3 V
0.2×V_DD
V
40
ns
40
ns
–
ns
10
–
–
ns
10
–
–
ns
10
–
–
ns
2002 Nov 04
24