SA2400A Datasheet, PDF (15/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
CURRENT
I_{ZOUT I2}
I₁
VOLTAGE
V₁
V₂
V_PH
I₂
I₁
Figure 4.
SR00602
12. FUNCTIONAL DESCRIPTION
12.1 Main Fractional-N divider
The divider consists of a fully programmable bipolar prescaler
followed by a CMOS counter. Total divide ratios range from 512 to
65535.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented by the value of NF.
The accumulator works with modulo Q set by FM (Synthesizer
Register A). When the accumulator overflows, the overall division
ratio N will be increased by 1 to N + 1, the average division ratio
over Q main divider cycles (either 5 or 8) will be
NF
Nfrac + N ) _Q
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
12.2 Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a 3-bit binary counter. The
3-bit SM register (see Figure 5) determines which of the five output
pulses are selected as the main phase detector input.
REFERENCE
INPUT
DIVIDE BY R
/2
/2
/2
/2
SM=“000”
SM=“001”
SM=“010”
SM=“011”
SM=“100”
Figure 5. Reference Divider
TO
MAIN
PHASE
DETECTOR
SR02354
2002 Nov 04
15