SA2400A Datasheet, PDF (22/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
Table 18. Address 04: Main chip operation modes, filter tuner, other controls
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
‘0000’
adc fterr Filttune v2p5 I1m I0p3 n.u. in22 clk xo digin rxlv veo vei Chip mode
Default 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
Bit #
0–3
Name
Chip mode
Description
Main mode of operation. Coding according to following table:
Bit3 Bit2 Bit1 Bit0 Mode
0
0
0
0
SLEEP
0
0
0
1
TX/RX
0
0
1
0
WAIT
0
0
1
1
RXMGC
0
1
0
0
FCALIB
0
1
0
1
DCALIB
0
1
1
0
FASTTXRXMGC
0
1
1
1
RESET
1
0
0
0
VCOCALIB
4
5
6
7
8
9
10
11
12
13
14
15–17
vei
veo
rxlv
digin
xo
clk
in22
Not used
I0p3
I1m
v2p5
filttune
18
fterr
19
adc
Notes on modes:
• All calibration modes (*CALIB) require the crystal oscillator to be ON (bit XO = 1).
• DCALIB (Tx LO leakage calibration) requires being in Tx mode for 5 µs before calibration.
Use external vco input (vcoextin)
Make internal vco available at vco pads (vcoextout)
Rx output common mode voltage: 0–V_DD/2, 1–1.25 V
Use digital Tx inputs (FIRDAC)
Xtal oscillator ON
Reference clock output ON
Xtal input frequency: 0–44 MHz, 1–22 MHz
External reference current (pad idcout): 0.3 mA to ground
External reference current (pad idcout): 1.0 mA from supply
External reference voltage (pad v2p5) ON
Rx and Tx filter tuning bits:
Write: (with test mode only), these bits set tuning value
Read: (in normal mode) tuner setting can be read out here
Filter tuner error (read only): result is 1 when tuner exceeded range
‘1’: in Rx mode, the RSSI-ADC is always on. ‘0’: the RSSI-ADC is only on during AGC operation.
Table 19. Address 05: AGC adjustment settings
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Name
Rx AGC target
Rx AGC Gmax
AGC_bbdel/ADCval
Default ±(0) val(000)
79 dB – 11001
7(1.3 µs) – 00111
98765
AGC_lnadel/sample2
15(2.7 µs) – 01111
43210
AGC_rxondel/sample1
27(4.9 µs) – 11011
Bit # Name
Description
0–4 AGC_rxondel/s1
Write: Programmable delay for AGC algorithm: Rx turn-on to AGCSET. In units of 182 ns (5.5 MHz)
Read: 1^st sample of RSSI in AGC cycle
5–9 AGC_lnadel/s2
Write: Programmable delay for AGC algorithm: Settling time after LNA gain switching. In units of 182 ns (5.5 MHz)
Read: 2^nd sample of RSSI in AGC cycle
10–14 AGC_bbdel/ADCval Write: Programmable delay for AGC algorithm: Settling time after baseband gain switching. In units of 182 ns
(5.5 MHz)
Read: Output of RSSI/Tx–peak detector ADC in 5-bit Gray code
15–19 AGC Gmax
Rx AGC gain limit (54 dB + programmed value) (valid: 54 through 85)
20–23 AGC target
Adjustment value to AGC settling target, range –7 dB … 7 dB (sign plus three bits)
2002 Nov 04
22