SA2400A Datasheet, PDF (18/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
13. SA2400A OTHER FUNCTIONALITY
Table 10 specifies functionality not described elsewhere in this document.
Table 10. SA2400A Other Functionality
T_amb = 25 °C; V_CC = 3.3 V
PARAMETER
Reference voltage output, pin V_2P5
Reference current output, pin IDCOUT
TEST CONDITIONS
Min
I_LOAD < 2 mA, C_LOAD < 10 pF;
switched on via register 0x04 bit 14 = ‘1’
2.25
Register 0x04 bit 12 = ‘1’;
0.25
“sink current” measured from supply to IC pin
Register 0x04 bit 13 = ‘1’;
0.85
“source current” measured from IC pin to ground
LIMITS
Typ
Max
2.5
2.75
0.3
0.35
1.0
1.15
UNITS
V
mA
mA
14. 3-WIRE BUS/LOGIC CONTROL
A simple 3-line bi-directional serial bus is used to program the
circuit. The 3 lines are SDATA, SCLK and SEN. The SDATA line is
bi-directional while the SCLK and SEN signals are always supplied
externally:
• The pin SEN is an “enable” signal. It is level sensitive: If SEN is of
LOW value, the 3-wire bus interface on the SA2400A is enabled.
This means that each rising edge on the SCLK pin (see below)
will be taken as a shift cycle, and address/data bits are expected
on SDATA (see below). If SEN is HIGH, the 3-wire bus interface
is disabled. No register settings will change regardless of activity
on SCLK and SDATA.
• The pin SCLK is the “shift clock” input. If the 3-wire bus is
enabled, address or data bits will be clocked in from the SDATA
pin with rising edges of SCLK. In output mode, SDATA bits are
set on the falling edge of SCLK in order to be sampled on the
rising edge by the controller.
• The pin SDATA is the bi-directional “data” pin. It is internally
configured as “input” or “output” depending on the operation
(WRITE or READ).
Each operation consists of 32 bits. Out of these, the first 7 bits form
an address word, followed by a READ/WRITE indicator bit. The
following 24 bits are the data word corresponding to the chosen
address.
The 3-wire bus interface contains an internal counter (state
machine) which determines beginning and end of address and data
word, the “write” pulse to the internal registers, and the direction of
the bi-directional SDATA pin. Consequently, with the 32^nd rising
SCLK edge of a WRITE cycle, the current data word is stored in the
internal register of the programmed address. Following SCLK edges
will be taken as the beginning of the following cycle. No
programming on SEN is needed to separate cycles.
If the SEN signal is switched to HIGH (i.e., DISABLE) at any time,
the current cycle will be disregarded. Any bits that have been shifted
in so far via SDATA will be disregarded. The internal counter is reset
to zero.
14.1 Description of WRITE cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
enabled.
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
The bit values on SDATA are taken over with rising edges on
SCLK.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising
edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.
4. (SCLK edges 9 through 32) 24 data bits are clocked in, LSB first,
with rising edges of SCLK. With the 32^nd rising edge of SCLK,
the whole data word is stored in the internal register according to
the selected address.
SCLK
SEN
SDATA
T_cyc
t_r
t_f
1
2
3
4
5
6
7
8
9
10
11
A0
A1
T_on
A2
A3
A4
A5
A6
R/W
D0
D1
D2
T_setup
T_hold
Figure 9. WRITE cycle timing diagram of the 3-wire bus
32
1
D23
SR02288
2002 Nov 04
18