SA2400A Datasheet, PDF (20/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
14.4 3-wire bus control register map
14.4.1 Data Format
Table 12. Format of programmed data
LAST IN (MSB)
FIRST IN (LSB)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 13. Overview
Address Description
00
Synthesizer: Main divider settings WRITE ONLY
01
Synthesizer: Reference divider and fractional compensation WRITE ONLY
02
Synthesizer: charge pump current and additional division WRITE ONLY
03
Synthesizer: test modes WRITE ONLY
04
Main operation modes, filter tuner, other controls
05
Rx AGC adjustment settings
06
Manual receiver control settings
07
Transmitter settings
08
VCO settings (only bits 0 through 9)
NOTES:
1. The synthesizer registers (addresses 00 to 03) cannot be read.
2. After programming register 0x01 it is necessary to also program register 0x00 to load the content of FC[7:0] into the internal working register.
3. After programming register 0x00 it is necessary to program some other register (e.g., 0x04) to avoid keeping the charge pump current
setting in php-speedup mode.
4. After running the VCOCALIB mode, it is necessary to re-program registers 0x00 through 0x03.
Table 14. Address 00: Synthesizer Register A
Note: Bits 22, 23 not used.
Main divider register
Bit
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
FM
NF[2:0]
N[15:0]
unused
Default 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0
Bit
FM
NF[2:0]
N[15:0]
Description
Fractional modulus select. 0–>/8; 1–>/5; default: 0
Fractional increment value (0 to 7); default: 4
Main divider division ration (512 to 65535); default: 615
Table 15. Address 01: Synthesizer Register B
Note: Bits 22, 23 not used.
Bit
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
R[9:0]
L
ON
FC[7:0]
Default
0000001011101101010000
Bit
R[9:0]
L[1:0]
ON
FC[7:0]
Description
Reference divider ratio (4 to 1023); default: 11
lock detect mode
00–> inactive
01–> inactive
10–>lock detect normal mode
11–>inactive
Power On/Off 1: as defined by chip mode (register 0x04) 0: inverted chip mode control
Fractional compensation charge pump current DAC (0 to 255); default: 80
2002 Nov 04
20