SA2400A Datasheet, PDF (19/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
14.2 Description of READ cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
enabled.
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
The bit values on SDATA are taken over with rising edges on
SCLK.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising
edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.
4. (SCLK edges 9 through 32) 24 data bits are clocked out, LSB
first. The bits will be available on the SDATA pin with the falling
edges of SCLK (so bits can be accepted by the baseband IC
with the following rising edge).
SCLK
SEN
T_cyc
t_r
t_f
1
2
3
4
5
6
7
8
9
10
11
32
1
SDATA
A0
A1
T_on
A2
A3
A4
A5
A6
R/W
D0
D1
D2
T_setup
T_dout
T_hold
Figure 10. READ cycle timing diagram of the 3-wire bus
D23
SR02289
The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new data even during power-down. The
data remains latched during power-down (sleep mode).
14.3 3-wire bus/logic control AC characteristics
Table 11. 3-wire bus/logic control AC characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
Serial Bus Logic Level Requirements
V_IH
HIGH logic input voltage
V_IL
LOW logic input voltage
Serial Programming Clock, SCLK
t_r
Input rise time
t_f
Input fall time
T_cyc
Clock period
Enable Programming, SEN
T_on
Delay to rising clock edge
Data Programming, SDATA
T_setup
Input data to clock set-up time
–
T_hold
Input data to clock hold time
–
T_dout
Output data to clock delay time
–
(falling edge)
LIMITS
UNITS
Min
Typ
Max
0.5×V_DD
–
–0.3
–
–
10
–
10
22
100
V_DD + 0.3 V
0.2×V_DD V
40
ns
40
ns
–
ns
10
–
–
ns
10
–
10
–
–
–
–
ns
–
ns
10
ns
2002 Nov 04
19