SA2400A Datasheet, PDF (10/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
9. SA2400A RECEIVER
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is
11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the
Receiver channel center frequency, as the IF output is at 0 Hz.
Table 6. SA2400A Receiver properties
T_amb = 25 °C; V_CC = 3.3 V; f_LO = 2.45 GHz.
Specification
Conditions
Min
Typ
Max
Units
RF input frequency range
S11 (RF input)
Maximum Rx voltage gain
Max RF input level
Typical
2.4
Incl balun+matching. 50 Ω unbalanced. Note 3.
LNA in high gain (see reg. description 0x06)
LNA in low gain
RF input to I or Q outputs
90
Including application, AGCTARGET = +5. Note 1. –10
To maintain nominal IQ output levels as defined
–20
below (“nominal I and Q output voltage”)
2.5
–10
–
–7
–
93
–
–
–
–
–
GHz
dB
dB
dB
dBm
dBm
IQ Output DC error (relative to signal, –80 dBm < P_input < –20 dBm, 1 MHz sinewave
–
5 µs after AGC set)
output. Note 3.
AGC settling time
(indicated by AGC_SET digital
output)
Initiated by AGC_RESET input. Constant RF input
within this settling time. Begins after TX to RX
switching time. Measured from AGC_RESET 0–1
transition. AGC delay registers (0x05) at default or
smaller values. Note 2.
a) First instance
–
b) 2^nd or subsequent instances
–
AGC Max Gain settling time
AGC forced to GMAX by:
a) TX to RX mode transition.
–
(measured after 5 µs TX–RX settling time).
b) Pulse on AGC_RESET pin
–
(measured from end of programming)
Note 2.
–
–20
dBc
–
8
µs
–
11
µs
–
0
µs
–
3
µs
AGC Max Gain adjustment range
Note 2.
54 to 85, in steps of 1
dB
AGC error (I, Q signal levels)
RF input between –75 to –20 dBm. AGC_RESET
used. AGC delay registers (0x05) at default values.
a) Random (varies each AGC cycle)
–3
–
3
dB
b) Slow (varies with V_CC, Temperature).
c) Static (fixed, part to part)
–1
–
1
dB
–1
–
1
dB
DC cancellation time
(after AGCRESET)
With constant RF input during this time. Note 3.
a) DC offset < 50% of output signal level
–
b) DC offset <10% of output signal level
–
–
8
µs
–
13
µs
TX to RX switching time
Output signal within 1 dB of final value,
–
frequency error within 25 ppm of final value. Note 3.
3
3.5
µs
Noise Figure
(Incl balun+matching)
Less than the piece-wise linear interpolation. Note 3.
P_input = –85 dBm (LNA in high gain mode)
–
–75 dBm
–
–60 dBm (LNA in low gain mode)
–
–45 dBm
–
7.5
9
dB
7.5
9
dB
24
25
dB
24
25
dB
Input IP3
(50 Ω source resistance)
2 interfering tones of power P_interferer each, at 13
–5
and 23 MHz offsets from LO.
IP3 to be more than the piece-wise linear
interpolation:
P_interferer = –39 dBm
1 dB compression of wanted signal Including matching, receiver at minimum gain.
–10
Desens by jammer
–45 dBm wanted signal at 1 MHz offset, +40 dBc
–
jammer at 25 MHz offset. Note 3.
1
–
0
–
–
1
dBm
dBm
dB
2002 Nov 04
10