SA2400A Datasheet, PDF (14/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
Specification
Conditions
Min
Typ
Max
Units
IQ input timing
Digital input selected, sampling on falling edge, Set-up time
–
4
–
ns
relative to REF_CLK_OUT
Hold time
–
4
–
ns
NOTES:
1. The 44 MHz common mode digital ground bounce on the I and Q inputs is assumed to be less than –30 dBc relative to signal level.
2. Verified by bench characterization and found to have sufficient margin for production.
3. The power ramping-up delay can be programmed to 2, 3, 4, 5 µs. See the 3-wire bus control register map. The default is 2 µs.
4. The differential input signal current is the difference between the I and /I (Q and /Q) instantaneous currents. The peak differential current is
therefore (I_max–I_min)/2 = 500 µA.
11. VCO AND SYNTHESIZER
Table 9 lists the synthesizer specifications. The synthesizer has the same specification as the SA8027 fractional PLL main loop without the PHI
speed-up mode. The phase comparator frequency used is typically 4 MHz (in fractional mode). The charge pump current is internally
programmed using the 3-wire bus (Synthesizer Register C). The recommended charge pump current is 480 µA. An external reference input of
44 MHz or 22 MHz is supported.
Table 9. Synthesizer and VCO Specifications
T_amb = 25 °C; V_CC = +3 V
PARAMETER
TEST CONDITIONS
LIMITS
Min
Typ
Max
UNITS
VCO
VCO output frequency range
2.4
–
2.5
GHz
VCO gain (K_VCO)
Open Loop VCO Phase Noise
V_tune = 1.2 V
70
Note 1. 1/f² roll off region; 0.5 MHz offset –
85
–113
100
–107
MHz/V
dBc/Hz
External VCO input levels
Differential; when device configured for
–10
–
0
external VCO
dBm
Main divider
N divider range
512
–
65535
Reference divider
Fixed reference input (XTAL_1 and XTAL_2)
frequency
–
22
–
–
44
–
MHz
MHz
R divider range (non-fractional)
SM = ‘000’
4
–
1023
Reference input level
Input parallel resistance (XTAL_1, XTAL_2)
XTAL_1 input
f = 44 MHz; indicative, not tested
350
–
10
–
1300
–
mV_pp
kΩ
Input parallel capacitance (XTAL_1, XTAL_2)
f = 44 MHz; indicative, not tested
–
–
1.5
pF
Phase detector
Phase detector frequency
–
–
4.0
MHz
Charge pump
Charge pump current accuracy
Charge pump compliance voltage
Output current variation vs. V_cp (Note 2)
Charge pump sink to source current
Matching
V_cp = 0.5 V_CC
V_cp in compliance range
V_cp = 0.5 V_CC
–20
–
0.6
–
–5
–
–10
–
+20
%
V_DD − 0.7 V
+5
%
+10
%
Charge pump “off” current leakage
V_cp = 0.5 V_CC
–5
±1
5
nA
NOTES:
1. This is measured at the Output1 RF port with the SA2400A in transmit mode, with static DC offset signals to the transmitter I and Q inputs.
The phase detector and divide-by-N phase noise is such that when configured as a phase locked loop with a 30 kHz loop band width, the
phase noise at frequencies between 1 kHz and 30 kHz will be no worse than –80 dBc/Hz. The total closed loop spur power within a 22 MHz
band around the carrier is less than –30 dBc.
2. The relative output current variation is defined as:
DI_ZOUT
I_OUT
+
2
with I₁ @ V₁ = 0.6 V, I₂ @ V₂ = V_CC – 0.7 V (see Figure 4).
(I₂ * I₁)
Ť _{I2 ) I1} Ť
2002 Nov 04
14