SA2400A Datasheet, PDF (17/34 Pages) NXP Semiconductors – Single chip transceiver for 2.45 GHz ISM band

Philips Semiconductors
Single chip transceiver for 2.45 GHz ISM band
Product data
SA2400A
12.4 Main output charge pumps and fractional
compensation currents (see Figure 7)
The main charge pumps on pin CP are driven by the main phase
detector and the charge pump current value is determined by bit CP
(Synthesizer Register C). The fractional compensation is derived
from the contents of the fractional accumulator FRD and by the
program value of the FDAC. The timing for the fractional
compensation is derived from the main divider. The charge pumps
will enter speed-up mode after sending a Synthesizer Register A
word and stays active until a different word is sent.
12.5 Principle of fractional compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I_COMP is the
compensation current and I_PUMP is the pump current:
I_{PUMP_TOTAL} = I_PUMP + I_COMP.
The compensation is done by sourcing a small current, I_COMP, see
Figure 8, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
Synthesizer B). The fractional compensation current is derived from
the main charge pump in that it follows all the current scaling through
programming or speed-up operation. For a given charge pump,
I_COMP = (I_PUMP / 128) * (FDAC / 5*128) * FRD
FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FM = 1 (modulo 5) and
80 for FM = 0 (modulo 8).
12.6 Lock Detect
The output LOCK maintains a logic ‘1’ when main phase detector
indicates a lock condition. The lock condition is defined as a phase
difference of less than 1 period of the frequency at the input
XTAL_1, XTAL_2. Out of lock (logic ‘0’) is indicated when the
synthesizer is powered down.
12.7 Power-down mode
The power-on signal is defined by the bit ON in Synthesizer Register
B. If ON = ‘1’, the synthesizer section is powered on/off as defined
by the chip mode (register 0x04). If ON = ‘0’, it is defined as inverted
to the chip mode. When the synthesizer is reactivated after
power-down, the main and reference dividers are synchronized to
avoid possibility of random phase errors on power-up.
REF. DIVIDER
OUTPUT R
MAIN DIVIDER
OUTPUT M
N
N
N+1
N
N+1
DETECTOR
OUTPUT
2
4
1
3
0
ACCUMULATOR
FRACTIONAL
COMPENSATION
CURRENT
PULSE
WIDTH
MODULATION
mA
OUTPUT ON
PUMP
µA
PULSE LEVEL
MODULATION
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 7. Waveforms for NF = 2 Modulo 5 → fraction = ²/₅
SR01416
f_RF
MAIN DIVIDER
FRACTIONAL
ACCUMULATOR
I_COMP
f_REF
Σ ^IPUMP
LOOP FILTER
& VCO
Figure 8. Current Injection Concept
SR01800
2002 Nov 04
17