OX9160 Datasheet, PDF (7/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
Multi-purpose & External interrupt pins
131 N/A 131 I/O
MIO0
N/A 131 N/A Z
130
I/O
129
I/O
Hi-Z
MIO1
MIO2
124-128
88-91
I
124-128
88-91
124-128
88-91
I/O
PME_In
MIO[11:3]
Multi-purpose I/O 0. Can drive high or low, or assert a PCI
interrupt
Permanent high impedance
Multi-purpose I/O 1. Can drive high or low, or assert a PCI
interrupt.
Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high or
low, or assert a PCI interrupt.
Input power management event. When LCC[7] is set this input pin
can assert a function1 PME#
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
Note 1: Direction key:
I
Input
IU
Input with internal pull-up
O
Output
I/O
Bi-directional
OD
Open drain
NC
No connect
Z
High impedance
P_I
P_O
P_I/O
P_OD
PCI input
PCI output
PCI bi-directional
PCI open drain
G
Ground
V
5.0V power
Note 2: Power & Ground
There are two GND and two VDD rails inside the device. One set of rails supply power and ground to output buffers while in
switching state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called
DC rail). The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and
undesirable RF radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI,
Local bus and parallel port pins.
Also, some GND pins (italicised) serve as GND in mode ‘00’ and mode ‘01’; however they are multiplexed and function as
address/data pins in mode ‘11’.
Data Sheet Revision 1.22
Page 7