OX9160 Datasheet, PDF (10/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
4.3 Accessing logical functions
Access to the local bus and parallel port is achieved via standard I/O and memory mapping, at addresses defined by the Base
Address Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and memory
space to the logical functions, according to which function is enabled and the size required. The addresses allocated can then be
used to access the functions. The mapping of these BARs is shown in Table 4.
BAR
Local bus
Parallel port
0
Local bus (I/O mapped)
Parallel port base registers (I/O mapped)
1
Local bus (memory mapped)
Parallel port extended registers (I/O mapped)
2
Local configuration registers (I/O mapped)
3
Local configuration registers (memory mapped)
4
Unused
5
Unused
Table 4: Base Address Register definition
4.3.1 PCI access to 8-bit local bus
BAR 0 and BAR 1 are used to access the Local bus. The
system allocates a block of I/O space and a block of
memory space according to the size requested.
I/O space
In order to minimise the usage of IO space, the block size
for BAR0 (I/O access) is user definable in the range of 4 to
256 bytes. Having assigned the address range, the user
can define two adjacent address bits to decode up to four
chip selects internally. This facility allows glueless
implementation of the local bus connecting to four external
peripheral chips. The address range and the lower address
bit for chip- select decoding (Lower-Address-CS-Decode)
are defined in the Local bus Configuration register (see
LT2[26:20] in section 1.1).
The 8-bit Local bus has eight address lines (LBA[7:0])
which correspond to the maximum IO address space. If the
maximum allowable block size is allocated to the IO space
(i.e. 256 bytes), then as access in IO space is byte aligned,
LBA[7:0] equal PCI AD[7:0] respectively. When the user
selects an address range which is less than 256 bytes, the
unused upper address lines will be set to logic zero.
The region can be divided into four chip-select regions
when the user selects the second uppermost non-zero
address bit for chip-select decoding. For example if 32-
bytes of IO space are reserved, the local bus address lines
A[4:0] are active and the remaining address lines are set to
zero. To generate four chip-selects the user should select
A3 as the Lower-Address-CS-Decode. In this case A[4:3]
will be used internally to decode chip-selects, asserting
LBCS0# when the address offset is 00-07h, LBCS1# when
offset is 08-0Fh, LBCS2# when offset is 10-17h, and
LBCS3# when offset is 18- 1Fh.
The region can be divided into two chip-select regions by
selecting the uppermost address bit to decode chip selects.
In the above example, the user can select A4 as the
Lower-Address-CS-Decode, thus using A[5:4] internally to
decode chip selects. As in this example LBA5 is always
zero, only chip-select lines LBCS0# and LBCS1# will be
decoded into, asserting LBCS0# when address offset is 00-
0Fh and LBCS1# when offset is 10-1Fh.
The region can be allocated to a single chip-select region
by assigning an address bit beyond the selected range to
Lower-Address-CS-Decode (but not above A8). In the
above example, if the user selects A5 as the Lower-
Address-CS-Decode, A[6:5] will be used to internally
decode chip-selects. As in this example LBA[7:5] are
always zero, only the chip select line LBCS0# may be
selected. In this case address offset 00-1Fh asserts
LBCS0# and the other chip-select lines remain inactive
permanently.
Memory Space:
The memory base address registers have an allocated
fixed size of 4K bytes in the address space. Since the
Local bus has 8 address lines and the OX9160 only
implements DWORD aligned accesses in memory space,
the 256 bytes of addressable space per chip select is
expanded to 1K. Unlike an I/O access, for a memory
access the unused upper address lines are always active
and the internal chip-select decoding logic ignores the user
setting for Lower-Address-CS-Decode (LT2[26:23]) and
uses PCI AD[11:10] to decode into 4 chip-select regions.
When the Local bus is accessed in memory space, A[9:2]
are asserted on LBA[7:0]. The chip-select regions are
defined in Table 5.
Data Sheet Revision 1.22
Page 10