OX9160 Datasheet, PDF (18/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
4.5 PCI Interrupts
Interrupts in PCI systems are level-sensitive and can be
shared. Interrupts can be triggered by the Parallel port, or
from the MIO pins when using the Local bus function. The
Parallel Port and MIO0 share the same interrupt status bit
(GIS[4]).
All interrupts in the OX9160 are routed to the PCI interrupt
pin, INTA#. During the system initialisation process and
PCI device configuration, system-specific software reads
the interrupt pin field to determine which (if any) interrupt
pin is used by each function. It programmes the system
interrupt router to logically connect this PCI interrupt pin to
a system-specific interrupt vector (IRQ). It then writes this
routing information to the Interrupt Line field in the
function’s PCI configuration space. Device driver software
must then hook ht e interrupt using the information in the
Interrupt Line field.
OX9160
Interrupt status for all the sources of interrupt is available
using the GIS register in the Local Configuration Register
set, which can be accessed using I/O or Memory
operations. This facility allows a device driver to quickly
ascertain the source of interrupt and service it. The
OX9160 also offers additional interrupt masking ability
using GIS[31:20] (see section 4.4.5), allowing drivers to
temporarily disable certain sources of interrupts
All interrupts can be enabled / disabled individually using
the GIS register set in the Local configuration registers.
When an MIO pin is enabled, an external device can assert
a PCI interrupt by driving that pin. The sense of the MIO
external interrupt pins (active-high or active-low) is defined
in the MIC register. The parallel port can also assert an
interrupt (Note: this effectively disables the MIO[0]
interrupt).
Data Sheet Revision 1.22
Page 18