OX9160 Datasheet, PDF (27/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
7.2.3 Zone2: Identification Registers
The Zone2 region of EEPROM contains the program value
for Vendor ID and Subsystem Vendor ID. The format of
Device Identification configuration WORDs are described in
Table 13.
Bits Description
15 ‘0’ = There are no more Zone2 (Identification)
bytes to program. Move to the next available
zone or end EEPROM program if no more zones
are enabled in the Header.
‘1’ = There is another Zone1 (Identification) byte
to follow.
14:8 0x00 = Vendor ID bits [7:0].
0x01 = Vendor ID bits [15:8].
0x02 = Subsystem Vendor ID [7:0].
0x03 = Subsystem Vendor ID [15:8].
0x03 to 0x7F = Reserved.
7:0 8-bit value of the register to be programmed
Table 13: Zone 2 data format
7.2.4 Zone3: PCI Configuration Registers
The Zone3 region of EEPROM contains any changes
required to the PCI Configuration registers (with the
exception of Vendor ID and Subsystem Vendor ID which
are programmed in Zone2). This zone consists of a
function header WORD, one or more configuration
WORDs, and a function end WORD. The function header
WORD is defined as 0x8001, and the end WORD is
defined as 0x0000.
The data between the function header WORD and the end
WORD consists of one or more configuration WORDs,
which contain the address offset and a byte of data for the
PCI Configuration Space of the function. The format of
configuration WORDs for the PCI Configuration Registers
are described below.
Bits Description
15 ‘0’ = This is the last configuration WORD.
‘1’ = There is another WORD to follow for this
function.
14:8 These seven bits define the byte-offset of the PCI
configuration register to be programmed. For
example the byte-offset of the Extended
Capabilities register is 0x06. Offset values are
tabulated in section 4.2.
7:0 8-bit value of the register to be programmed
Table 14: Zone 3 data format (data)
Table 15 shows which PCI Configuration registers are
writable from the EEPROM.
Offset Bits Description
0x02 7:0 Device ID bits 7 to 0.
0x03 7:0 Device ID bits 15 to 8.
0x06 3:0 Must be ‘0000’.
0x06 4 Extended Capabilities.
0x06 7:5 Must be ‘000’.
0x09 7:0 Class Code bits 7 to 0.
0x0A 7:0 Class Code bits 15 to 8.
0x0B 7:0 Class Code bits 23 to 16.
0x2E 7:0 Subsystem ID bits 7 to 0.
0x2F 7:0 Subsystem ID bits 15 to 8.
0x42 7:0 Power Management Capabilities
bits 7 to 0.
0x43 7:0 Power Management Capabilities
bits 15 to 8.
Table 15: EEPROM-writable PCI configuration registers
Table 16 shows an example zone 3 which sets the device
ID with two configuration words.
Description
Function header word
Set Device ID[7:0] – one more config word
Set Device ID[15:8] – no more config words
end WORD
Data
0x8001
0x82CD
0x03AB
0x0000
Table 16: Example zone 3 data
Data Sheet Revision 1.22
Page 27