OX9160 Datasheet, PDF (12/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
4.4 Accessing Local configuration registers
The local configuration registers are a set of device specific registers which are used to configure the controller. They are
mapped to the I/O and memory addresses set up in BAR2 and BAR3, with the offsets defined for each register. Access is limited
to byte only for I/O accesses; memory accesses can also be word or dword accessed, however on little-endian systems such as
Intel 80x86 the byte order will be reversed.
4.4.1 Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial
EEPROM. The individual bits are described below.
Bits
Description
Read/Write
Reset
EEPROM
PCI
1:0
Mode. These bits return the state of the Mode[1:0] pins.
-
R
XX
2
Enable crystal clock output. When this bit is set, the crystal oscillator
W
RW
0
output pin (XTL_Ck_Out) is active. When low, XTL_Ck_Out is
permanently low.
4:3
Endian Byte-Lane Select for memory access to 8-bit Local bus.
W
RW
00
00 = Select Data[7:0]
10 = Select Data[23:16]
01 = Select Data[15:8]
11 = Select Data[31:24]
Memory access to OX9160 is always DWORD aligned. When accessing
8-bit regions like the 8-bit Local bus and the parallel port, this option
selects the active byte lane. As both PCI and PC architectures are little
endian, the default value will be used by systems, however, some non-
PC architectures may need to select the byte lane. These bits are
ignored in 32-bit Local bus.
6:5
Reserved. These bits are used for test purposes. The device driver must
-
R
00
write zeros to these bits.
7
MIO2_PME Enable. A value of ‘1’ enables the MIO2 pin to set the
W
RW
0
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO2 from setting the PME_Status bit
(see section 4.6).
23:8
Reserved. These bits are used for test purposes. The device driver must
-
R
0000h
write zeros to these bits.
24
EEPROM Clock. For PCI read or write to the EEPROM , toggle this bit to
-
RW
0
generate an EEPROM clock (EE_CK pin).
25
EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
-
RW
0
activated (high). When 0 EE_CS is de-active (low).
26
EEPROM Data Out. For writes to the EEPROM, this output bit is the
-
RW
0
input-data of the EEPROM. This bit is output on EE_DO and clocked into
the EEPROM by EE_CK.
27
EEPROM Data In. For reads from the EEPROM, this input bit is the
-
R
X
output-data of the EEPROM connected to EE_DI pin.
28
EEPROM Valid. A 1 indicates that a valid EEPROM program is present
-
R
X
29
Reload configuration from EEPROM. Writing a 1 to this bit re-loads the
-
RW
0
configuration from EEPROM. This bit is self-clearing after EEPROM read
30
Reserved
-
-
0
31
Reserved
-
R
0
Data Sheet Revision 1.22
Page 12