OX9160 Datasheet, PDF (19/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
4.6 Power Management
The OX9160 is compliant with PCI Power Management
Specification Revision 1.0. The local bus can recognise
power states D0, D2 and D3. Power management is
accomplished by power-down and power-up requests,
asserted via interrupts and the PME# pin respectively. The
device can assert to the PME# pin to request that the
system ‘wake up.’ The PME# pin is de-asserted when the
sticky PME_Status bit is cleared.
Power-down request is not defined by Power Management
1.0. It is a device-specific feature and requires a bespoke
device driver implementation.
The PME# pin can, in certain cases, activate the PME#
signal when power is removed from the device, which will
cause the PC to wake up from Low-power state D3(cold).
To ensure full cross-compatibility with systemboard
implementations, use of an isolator FET is recommended.
If Power Management capabilities are not required, the
PME# pin can be treated as no-connect.
The power-down request for the Local bus is application-
dependent. The device driver can use any of the multi-
purpose I/O lines, MIO[12:3] to issue a power-down
request.
The Local bus implements the PCI Power Management
power-states D0, D2 and D3. Whenever the device driver
changes the power-state to state D2 or D3, the device
takes the following actions:-
• The external XTL_Ck_Out pin is disabled regardless
of the programmed value in LCC[2].
• The Local bus clock pin, LBCK, is disabled regardless
of the programmed value in LT2[30].
• The PCI interrupt is disabled.
• Access to I/O or Memory BARs is disabled.
However, access to the configuration space is still enabled.
The device driver can optionally assert/de-assert any of its
selected (design dependant) MIO pins to switch off VCC,
disable other external clocks, or activate shut-down modes
to any external devices on the Local bus.
Devices on the local bus can issue a wake up request by
using the MIO2 pin. When LCC[7] is set, a rising or falling
edge of MIO2 will cause the OX9160 to issue a wake up
request by setting PME_Status = (PMCSR[15]), if it is
enabled by PMCSR[8]. When LCC[7] is set, the MIO2 pin
will remain in input mode regardless of the value
programmed in MIC[5], However MIC[4] still controls the
input sense. PME_Status is a sticky bit which will be
cleared by writing a ‘1’ to it. While the PME_En
(PMCSR[8]) bit is set, PME_Status will assert the PME#
pin to inform the device driver that a power management
wake up event has occurred. After a wake up event is
signalled, the device driver is expected to return the
function to the D0 power-state. Settings for wake up events
are shown in Table 7.
LCC[7]
0
1
1
1
1
MIC[4]
X
0
0
1
1
MIO2 Rising
X
yes
no
X
X
MIO2 Falling
X
X
X
Yes
No
PME_Status
Remains unchanged
Gets set
Remains unchanged
Gets set
Remains unchanged
Table 7: Local bus Wake-up configuration
Data Sheet Revision 1.22
Page 19