OX9160 Datasheet, PDF (21/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
5.3 Configuration & Programming
The configuration registers for the local bus controller are
described in sections 4.4.3 & 4.4.4. The values of these
registers after reset allow the host system to identify the
function and configure its base address registers.
Alternatively many of the default values can be re-
programmed during device initialisation through use of the
optional serial EEPROM (see section 7).
The I/O space block can be varied in size from 4 bytes to
256 bytes (32 bytes is the default) by setting LT2[22:20]
accordingly. Varying the block size means that I/O space
can be allocated efficiently by the system, whatever the
application.
The I/O block can then be divided into one, two or four
chip-select regions, depending on the setting in LT2[26:23].
To divide the area into four chip-select region, the user
should select the second uppermost non-zero address bit
as the Lower-Address-CS-decode. To divide into two
regions, the user should select the uppermost address bit.
If an address bit beyond the selected range is selected, the
entire I/O space is allocated to CS0#. For example, if 32
bytes of I/O space are reserved, the active address lines
are A[4:0]. To divide this into four regions, the Lower
Address CS parameter should be set to A3, by
programming the value ‘0001’ into LT2[26:23]. To select
two regions, choose A4, and to maintain one region, select
any value greater than A4.
In 8-bit mode, the memory space block is always 4K bytes,
and always divided into four chip-select regions of 1K byte
each.
In 32-bit mode, again the I/O space can be varied in size
from 4 bytes to 256 bytes. It is also possible to increase the
memory space block size from 4K bytes to 16K bytes. Also
in 32-bit mode, the Lower-Address-CS-Decode parameter
afftects division of the I/O space AND memory space into
chip-select regions.
A soft reset facility is provided so software can
independently reset the peripherals on the local bus. The
local bus reset signals, LBRST and LBRST#, are always
active during a PCI bus reset and also when the
configuration register bit LT2[29] is set to 1.
OX9160
5.4 Clock references
The clock enable bit LT2[30], when set enables a copy of
the PCI bus clock output on the local bus pin LBCLK. If a
reference clock is desired this signal should be used as
splitting the PCICLK signal will violate the PCI
specification.
A buffered crystal clock can also be asserted on the
XTL_Ck_Out pin; this means that a single oscillator can be
used to drive devices such as UARTs on the local bus. To
make use of the XTL_Ck_Out function, a crystal oscillator
circuit should be connected to the XTLI and XTLO pins, as
shown in Figure 3.
XTLO
R₂
C₁
R₁
XTLI
C2
Figure 3: Crystal Oscillator Circuit
Frequency
Range
(MHz)
1-8
8-60
C1
C2 (pF)
(pF)
R1 (Ω )
68
22
220k
33-68 33 – 68 220k-2M2
Table 8: Component values
R2 (Ω )
470R
470R
Note: For better stability use a smaller value of R1.
Increase R1 to reduce power consumption.
The total capacitive load (C1 in series with C2) should be
that specified by the crystal manufacturer (nominally 16pF).
Data Sheet Revision 1.22
Page 21