OX9160 Datasheet, PDF (17/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
LT2[15:0] enable the card designer to control the data bus during the idle periods. The default values will configure the Local bus
data pins to remain forcing (LT2[7:4] = Fh). LT[15:8] is programmed to place the bus in high-impedance at the beginning of a
read cycle and set it back to forcing at the end of the read cycle. For systems that require the data bus to stay in high-
impedance, the card designer should write an appropriate value in the range of 0h to Ah to LT2[7:4]. This will place the data bus
in high impedance at the end of the write cycle. Whenever the value programmed in LT2[7:4] does not equal Fh, the Local bus
controller will ignore the setting of LT2[15:8] as the data bus will be high-impedance outside write cycles. In this case the card
designer should place external pull-ups on the data bus pins LBD[7:0] (or LBD[32:0] in 32-bit mode).
While the configuration data is read from the external EEPROM, the LBD pins remain in the high-impedance state.
The timing registers define the Local bus timing parameters based on signal changes relative to a reference cycle which is
defined as two PCI clock cycles after IRDY# is asserted for the first time in a frame. The following parameters are fixed relative to
the reference cycle.
The Local bus address pins (LBA[7:0] in 8-bit Local bus, LBA[15:0] in 32-bit Local bus) are asserted during the reference cycle.
In a write operation, the Local bus data is available during the reference cycle, however I/O buffers change direction as
programmed in LT2[3:0]. In a Motorola type bus write operation, the Read-not- Write pin (LBRDWR#) is asserted (low) during the
reference cycle. In a read cycle this pin remains high throughout the duration of the operation.
The default settings in LT1 & LT2 registers provide one PCI clock cycle for address and chip-select to control signal set-up time,
one clock cycle for address and chip-select from control signal hold time, two clock cycles of pulse duration for read and write
control signals and one clock cycle for data bus hold time. These parameters are acceptable for using external OX16C950,
OX16C952 and OX16C954 devices connected to the Local bus, in Intel mode. Some redefinition will be required if the bus is to
be operated in Motorola mode.
The user should take great care when programming the Local bus timing parameters. For example defining a value for chip-
select assertion which is larger that the value defined for chip- select de-assertion or defining a chip-select assertion value which
is greater than control signal assertion will result in obvious invalid local Bus cycles.
4.4.5 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C)
Bits Description
Read/Write
EEPROM _PCI
3:0 Reserved
-
R
4
MIO0 (Mode[1:0]≠‘01’). This bit reflects the state of the internal MIO[0]. The -
R
internal MIO[0] reflects the non-inverted or inverted state of MIO0 pin.¹
Reset
0x0h
X
15:5
19:16
20
Parallel Port Interrupt (Mode[1:0]=‘01’). This bit reflects the state of the Parallel
Port internal interrupt line.
-
These bits reflect the state of the internal MIO[11:2]. The internal MIO[11:2] -
reflect the non-inverted or inverted state of MIO[11:2] pins respectively.¹
Reserved.
-
MIO[0] Interrupt Mask (Mode[1:0]≠‘01’). When set (=1) this bit enables MIO0 W
pin to assert a PCI interrupt. When cleared (=0) it prevents MIO0 pin from
asserting a PCI interrupt.¹
R
0
R
XXXh
R
Fh
RW
1
31:21
Parallel Port Interrupt Mask (Mode[1:0]=‘01’). When set (=1) this bit enables W
the Parallel Port to assert a PCI interrupt. When cleared (=0) it prevents the
Parallel Port from asserting a PCI interrupt.
MIO Interrupt Mask. When set (=1) these bits enable each MIO[11:1] pin to W
assert a PCI interrupt respectively. When cleared (=0) they prevent the
respective pins from asserting a PCI interrupt.¹
RW
1
RW
7FFh
Note 1:
The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register
‘MIC’ (offset 0x14). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as active-low
or active-high, as controlled by the MIC register.
Data Sheet Revision 1.22
Page 17