OX9160 Datasheet, PDF (2/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
CONTENTS
1 BLOCK DIAGRAM .......................................................................................................................3
2 PIN INFORMATION .....................................................................................................................4
3 PIN DESCRIPTIONS ....................................................................................................................5
4 PCI TARGET CONTROLLER .......................................................................................................8
4.1 OPERATION.......................................................................................................................................................................... 8
4.2 CONFIGURATION SPACE ................................................................................................................................................... 8
4.2.1 PCI CONFIGURATION SPACE REGISTER MAP ........................................................................................................... 9
4.3 ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 10
4.3.1 PCI ACCESS TO 8-BIT LOCAL BUS ............................................................................................................................. 10
4.3.2 PCI ACCESS TO 32-BIT LOCAL BUS ........................................................................................................................... 11
4.3.3 PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11
4.4 ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12
4.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ......................................................... 12
4.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................. 13
4.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): ................................................................... 14
4.4.4 LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): .................................................................. 16
4.4.5 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 17
4.5 PCI INTERRUPTS ............................................................................................................................................................... 18
4.6 POWER MANAGEMENT.................................................................................................................................................... 19
5 LOCAL BUS ..............................................................................................................................20
5.1 OVERVIEW.......................................................................................................................................................................... 20
5.2 OPERATION........................................................................................................................................................................ 20
5.3 CONFIGURATION & PROGRAMMING ............................................................................................................................. 21
5.4 CLOCK REFERENCES ...................................................................................................................................................... 21
6 BIDIRECTIONAL PARALLEL PORT...........................................................................................22
6.1 OPERATION AND MODE SELECTION ............................................................................................................................. 22
6.1.1 SPP MODE...................................................................................................................................................................... 22
6.1.2 PS2 MODE...................................................................................................................................................................... 22
6.1.3 EPP MODE...................................................................................................................................................................... 22
6.1.4 ECP MODE (NOT SUPPORTED)................................................................................................................................... 22
6.2 PARALLEL PORT INTERRUPT ......................................................................................................................................... 22
6.3 REGISTER DESCRIPTION................................................................................................................................................. 23
6.3.1 PARALLEL PORT DATA REGISTER ‘PDR’................................................................................................................... 23
6.3.2 DEVICE STATUS REGISTER ‘DSR’.............................................................................................................................. 23
6.3.3 DEVICE CONTROL REGISTER ‘DCR’ .......................................................................................................................... 24
6.3.4 EPP ADDRESS REGISTER ‘EPPA’............................................................................................................................... 24
6.3.5 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................... 24
6.3.6 EXTENDED CONTROL REGISTER ‘ECR’ .................................................................................................................... 24
7 SERIAL EEPROM......................................................................................................................25
7.1 SPECIFICATION ................................................................................................................................................................. 25
7.2 EEPROM DATA ORGANISATION ..................................................................................................................................... 25
7.2.1 ZONE0: HEADER............................................................................................................................................................ 25
7.2.2 ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 26
7.2.3 ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 27
7.2.4 ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 27
8 OPERATING CONDITIONS ........................................................................................................28
9 DC ELECTRICAL CHARACTERISTICS ......................................................................................28
Data Sheet Revision 1.22
Page 2