OX9160 Datasheet, PDF (14/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
Bits
19:18
21:20
23:22
31:24
Description
01 -> MIO8 is an inverting input pin
10 -> MIO8 is an output pin driving ‘0’
11 -> MIO8 is an output pin driving ‘1’
MIO9 Configuration Register.
00 -> MIO9 is a non-inverting input pin
01 -> MIO9 is an inverting input pin
10 -> MIO9 is an output pin driving ‘0’
11 -> MIO9 is an output pin driving ‘1’
MIO10 Configuration Register.
00 -> MIO10 is a non- inverting input pin
01 -> MIO10 is an inverting input pin
10 -> MIO10 is an output pin driving ‘0’
11 -> MIO10 is an output pin driving ‘1’
MIO11 Configuration Register.
00 -> MIO11 is a non- inverting input pin
01 -> MIO11 is an inverting input pin
10 -> MIO11 is an output pin driving ‘0’
11 -> MIO11 is an output pin driving ‘1’
Reserved
OX9160
Read/Write
EEPROM
PCI
Reset
W
RW
00
W
RW
00
W
RW
00
-
R
00h
4.4.3 Local bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the Local bus. The
timing parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local bus control signals. The
value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur,
where the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The following arrangement
provides a flexible approach for users to define the desired bus timing of their peripheral devices. The timings refer to I/O or
Memory mapped access to BAR0 and BAR1 respectively.
Bits
Description
3:0
Read Chip-select Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a read operation from the Local bus.¹
These bits are unused in Motorola- type interface.
7:4
Read Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
de-asserted (high) during a read from the Local bus. ¹
These bits are unused in Motorola- type interface.
11:8
Write Chip-select Assertion (Intel- type interface). Defines the number of
clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a write operation to the Local bus. ¹
These bits are unused in Motorola- type interface.
Data Sheet Revision 1.22
Read/Write
EEPROM _PCI
W
RW
Reset
0h
W
RW
3h
(2h for
parallel port)
W
RW
0h
Page 14