OX9160 Datasheet, PDF (11/38 Pages) Oxford Semiconductor – PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus

OXFORD SEMICONDUCTOR LTD.
OX9160
Local bus
Chip-Select
(Data-Strobe)
LBCS0# (LBDS0#)
LBCS1# (LBDS1#)
LBCS2# (LBDS2#)
LBCS3# (LBDS3#)
PCI Offset from BAR 1
(Memory space)
Lower Address Upper Limit
000h
3FCh
400h
7FCh
800h
BFCh
C00h
FFCh
Table 5: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses
is for an Intel- type configuration for the Local bus. For
Motorola-type configuration, the chip select pins are
redefined to data strobe pins. In this mode the Local bus
offers up to 8 address lines and four data-strobe pins.
4.3.2 PCI access to 32-bit local bus
Access to the Local bus in 32-bit mode is similar to 8-bit
mode (see section 4.3.1) with the following exceptions:
• The local Bus offers a 32-bit bi-directional data bus
and 12 bit address bus
• The PCI address signals ‘AD[13:2]’ are asserted on
LBA[11:0]
• Block size in memory space is programmable by
LT2[28:27] (see section 1.1)
• The Lower-Address-CS-Decode (LT2[26:23])
parameter is used to decode up to 4 chip selects
The block size allocation for chip-select regions is defined
in Table 6.
Number
of Chip
selects
1
2
4
1
2
4
Memory
block size
(Kbytes)
16
16
16
4
4
4
LT2[28:27] LT2[26:23]
‘01’
‘1010’
‘01’
‘1001’
‘01’
‘1000’
‘00’
‘1000’
‘00’
‘0111’
‘00’
‘0110’
Table 6: PCI access to 32-bit local bus (memory)
4.3.3 PCI access to parallel port
When the parallel port is enabled (Mode 01), access to the
port works via BAR definitions as usual, except that there
are two I/O BARs corresponding to two sets of registers
defined to operate a bi-directional Parallel Port. Memory
mapped access to the parallel port is not supported.
The user can change the I/O space block size of BAR0 by
over-writing the default values in LT2[25:20] using the
serial EEPROM (see section 1.1). For example the user
can reduce the allocated space for BAR0 to 4-bytes by
setting LT2[22:20] to ‘001’. The I/O block size allocated to
BAR1 is fixed at 8-Bytes.
Legacy PC parallel ports expect the upper register set to
be mapped 0x400 above the base block, therefore if the
BARs are fixed with this relationship, generic parallel port
drivers can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
Data Sheet Revision 1.22
Page 11