ADP3210 Datasheet, PDF (5/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

Parameter
PWM Clock Frequency
Symbol
fCLK
RAMP GENERATOR
RAMP Voltage
RAMP Current Range²
PWM COMPARATOR
PWM Comparator Offset²
RPM COMPARATOR
RPM Current
RPM Comparator Offset²
CLOCK SYNC
Trigger Threshold²
VRAMP
IRAMP
VOSRPM
IRPM
VOSRPM
TRDET#
Trigger Threshold²
TRDET# Low Voltage²
TRDET# Leakage Current²
SWITCH AMPLIFIER
SW Common Mode Range²
SW Input Resistance
ZERO CURRENT SWITCHING
COMPARATOR
SW ZCS Threshold
Masked Off-Time
SYSTEM I/O BUFFERS
VID[6:0], DPRSLP, PSI# INPUTS
Input Voltage
VLTRDET
IHTRDET
VSW(X)CM
RSW(X)
VDCM(SW1)
tOFFMSKD
Input Current
VID Delay Time²
EN INPUT
Input Voltage
Input Current
Conditions
TA = +25°C, VVID = 1.2000 V
RT = 73 kΩ²
RT = 125 kΩ²
RT = 180 kΩ
EN = H, IRAMP = 60 μA
EN = L
EN = H
EN = L, RAMP = 19 V
VOSPWM = VRAMP − VCOMP
VVID = 1.2 V, RT = 180 kΩ
See also IRPM(RT) formula
VOSRPM = VCOMP − (1 +VRPMTH)
Relative to COMP sampled TCLK earlier
3-ph configuration
2-phase configuration
1-phase configuration
Relative to COMP sampled TCLK earlier
3-ph configuration
2-phase configuration
1-phase configuration
Logic low, ICLKENsink = 4mA
Logic high, VTRDET# = VCC
SWX = 0 V
In DCM mode, DPRSLP = 3.3 V
Measured from PWM neg edge to pos edge
Refers to input (driving) signal level
Logic low, ISINK ≥ 1 μA
Logic high, ISOURCE ≤ −5 μA
V = 0.2 V
VID[6:0], DPRSLP (active pull down to GND)
PSI# (active pull-up to VCC)
VID any edge to FB change 10%
Refers to input (driving) signal level
Logic low, ISINK ≥ 1 μA
Logic high, ISOURCE ≤ −5 μA
EN = L or EN = H (static)
0.8 V < EN < 1.6 V (during transition)
Rev. 0.3 | Page 5 of 38
ADP3210
Min Typ Max Units
1000
700
500
1300
800
600
1600 kHz
900 kHz
780 kHz
0.9
1
1.1 V
VIN
V
1
100 μA
−0.5
+0.5 μA
−3
+3 mV
−6.1
μA
−3
+3 mV
350
mV
400
mV
450
mV
−450
−500
−600
30
mV
mV
mV
300 mV
3 μA
−600
+200 mV
20
35
50 kΩ
−6
mV
650
ns
0.7
−1
+2
200
V
0.3 V
μA
μA
ns
0.3 V
1.8
V
10
nA
70
μA