ADP3210 Datasheet, PDF (28/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
360 nH × 220 mV
( ) ^{C x(MAX) ≤} 2 × 3.1² × 2.1 mΩ ² × 1.150 V
⎜⎛
⎜
⎜⎝
1
+
⎜⎛
⎜⎝
22
μ
s
×
1.150 V × 2 × 3.1 ×
220 mV × 360 nH
2.1
mΩ
⎟⎞
⎟⎠
2
⎟⎞
−1_⎟ − 320 μF
⎟⎠
= 2.3 mF
Using four 330 μF Panasonic SP capacitors with a typical ESR of
6 mΩ each yields C_X = 1.32 mF with an R_X = 1.5 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change. This is tested using
L_x ≤ C_z × RO2×Q²
( ) L_x ≤ 320 μ F × 2.1 mΩ ² × 2 = 2nH
(16)
where:
Q is limited to the square root of 2 to ensure a critically damped
system.
In this example, L_X is about 250 pH for the four SP capacitors,
which satisfies this limitation. If the LX of the chosen bulk
capacitor bank is too large, the number of ceramic capacitors
may need to be increased if there is excessive ringing.
Note that for this multimode control technique, an all-ceramic
capacitor design can be used as long as the conditions of
Equation 13, Equation 14, and Equation 15 are satisfied.
POWER MOSFETS
For normal 20 A per phase application, the N-channel power
MOSFETs are selected for two high-side switches and two low-
side switches per phase. The main selection parameters for the
power MOSFETs are V_GS(TH), Q_G, C_ISS, C_RSS and R_DS(ON). Because
the gate drive voltage (the supply voltage to the ADP3611) is
5 V, logic-level threshold MOSFETs must be used.
The maximum output current I_O determines the R_DS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3210, currents are balanced between phases; the current in
each low-side MOSFET is the output current divided by the
total number of MOSFETs (n_SF). With conduction losses being
dominant, the following equation shows the total power
dissipated in each synchronous MOSFET in terms of the ripple
current per phase (I_R) and average total output current (I_O):
P_SF
=
(1
−
D
)
×
⎢⎢⎣⎡⎜⎜⎝⎛
I_O
n_SF
⎟⎟⎠⎞²
+
1
12
×
⎜⎜⎝⎛
n×I
n_SF
R
⎟⎟⎠⎞²
⎤
⎥
⎥⎦
×
R_DS(SF
)
(17)
Knowing the maximum output thermal current and the
maximum allowed power dissipation, users can find the
required R_DS(ON) for the MOSFET. For 8-lead SOIC or 8-lead
SOIC compatible packaged MOSFETs, the junction to ambient
(PCB) thermal impedance is 50°C/W. In the worst case, the
PCB temperature is 90°C during heavy load operation of the
notebook; a safe limit for PSF is 0.6 W at 120°C junction
temperature. Thus, for this example (32 A maximum thermal
current), R_DS(SF) (per MOSFET) is less than 9.6 mΩ for two
pieces of low-side MOSFET. This RDS(SF) is also at a junction
temperature of about 120°C; therefore, the RDS(SF) (per
MOSFET) should be lower than 6.8 mΩ at room temperature,
giving 9.6 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of
feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components, conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, Equation 18
provides an approximate value for the switching loss per main
MOSFETs
P_{S( MF)}
=2×
f _SW
× ^{VCC × IO}
n_MF
× R_G
× ^nMF
n
× C_ISS
(18)
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance (1.5 Ω for the ADP3419 and about
0.5 Ω for two pieces of typical high speed switching MOSFETs,
making RG = 2 Ω).
CISS is the input capacitance of the main MOSFET. The best
thing to reduce switching loss is to use lower gate capacitance
devices.
The conduction loss of the main MOSFET is given by
P_{C(MF )}
=
D
×
⎢⎢⎣⎡⎜⎜⎝⎛
I_O
n _MF
⎟⎟⎠⎞ ²
+
1
12
×
⎜⎜⎝⎛
n×I_R
n _MF
⎟⎟⎠⎞
2
⎤
⎥
⎥⎦
×
R _DS(
MF
)
(19)
where:
RDS(MF) is the on-resistance of the MOSFET.
Typically, for main MOSFETs, users want the highest speed (low
C_ISS) device, but these usually have higher on-resistance. Users
must select a device that meets the total power dissipation
(0.6 W for a single 8-lead SOIC package) when combining the
switching and conduction losses.
Rev. 0.3 | Page 28 of 38