ADP3210 Datasheet, PDF (34/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
V_{TRANRE L}
V_DROOP
for the CSSUM node.) The MLCC for the VCC decoupling
should be placed as close to the VCC pin as possible. In
addition, the noise filtering cap on the TTSENSE pin should
also be as close to that pin as possible.
The output capacitors should be connected as closely as possible
to the load (or connector) that receives the power (for example,
a microprocessor core). If the load is distributed, then the
capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic.
Figure 30. Transient Setting Waveform, Load Release
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
For effective results, at least a four-layer PCB is recommended.
This allows the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the rest of the power delivery current paths. Note that
each square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
When high currents need to be routed between PCB layers, vias
should be used liberally to create several parallel current paths so
that the resistance and inductance introduced by these current
paths are minimized, and the via current rating is not exceeded.
If critical signal lines (including the output voltage sense lines of
the ADP3210) must cross through power circuitry, then a signal
ground plane should be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground a bit noisier.
An analog ground plane should be used around and under the
ADP3210 for referencing the components associated with the
controller. Tie this plane to the nearest output decoupling
capacitor ground. It should not be tied to any other power
circuitry to prevent power currents from flowing in it.
The best location for the ADP3210 is close to the CPU corner
where all the related signal pins are located: VID0 to VID6, PSI,
VCCSENSE, and VSSSENSE.
The components around the ADP3210 should be located close to
the controller with short traces. The most important traces to keep
short and away from other traces are the FB and CSSUM pins (refer
to Error! Reference source not found. for more details on layout
Power Circuitry
Avoid crossing any signal lines over the switching power path
loop. This path should be routed on the PCB to encompass the
shortest possible length in order to minimize radiated switching
noise energy (that is, EMI) and conduction losses in the board.
Failure to take proper precautions often results in EMI
problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs,
including all interconnecting PCB traces and planes. The use of
short and wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the switching
loop, which can cause high energy ringing, and it accommodates
the high current demand with minimal voltage loss.
Whenever a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. Make a mirror image of any pad
being used to heat sink the MOSFETs on the opposite side of
the PCB to achieve the best thermal dissipation to the air
around the board. To further improve thermal performance, the
largest possible pad area should be used.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
For best EMI containment, use a solid power ground plane as one
of the inner layers extending fully under all the power components.
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