ADP3210 Datasheet, PDF (14/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
THEORY OF OPERATION
The ADP3210 combines a multimode PWM/RPM (ramp pulse
modulated) control with multiphase logic outputs for use in 1-,
2-, and 3-phase synchronous buck CPU core supply power
converters. The internal 7-bit VID DAC conforms to Intel
IMVP-6.5 specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling high currents in a single-
phase converter puts high thermal stress on the system
components such as the inductors and MOSFETs.
The multimode control of the ADP3210 ensures a stable high
performance topology for:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and minimal output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
• Tight load line regulation and accuracy
• High current output by supporting up to 3-phase operation
• Reduced output ripple due to multiphase ripple cancellation
• High power conversion efficiency both at heavy load and
light load
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation by allowing optimization of design
for low cost or high performance
NUMBER OF PHASES
The number of operational phases and their phase relationship
is determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3210 operates as a 3-phase
controller. For 2-phase operation, the PWM3 pin is connected
to VCC 5 V, and for 1-phase operation, the PWM3 and PWM2
pins are connected to VCC 5 V.
When the ADP3210 is initially enabled, the controller sinks 50 μA
on the PWM2 and PWM3 pins. An internal comparator checks
the voltage of each pin against a high threshold of 3 V. If the pin
voltage is high due to pull up to the VCC 5 V rail, then the
phase is disabled. The phase detection is made during the first
three clock cycles of the internal oscillator. After phase detection,
the 50 μA current sink is removed. The pins that are not connected
to the VCC 5 V rail function as normal PWM outputs. The pins
that are connected to VCC enter into high impedance state.
The PWM outputs are 5 V logic-level signals intended for
driving external gate drivers such as the ADP3611. Because
each phase is monitored independently, operation approaching
100% duty cycle is possible. In addition, more than one output
can operate at a time to allow overlapping phases.
OPERATION MODES
For ADP3210, the number of phases can be selected by the user
as described in the Number of Phases section, or they can
dynamically change based on system signals to optimize the
power conversion efficiency at heavy and light CPU loads.
During a VID transient or at a heavy load condition, indicated
by DPRSLP going low and PSI going high, the ADP3210 runs
in full-phase mode. All user selected phases operate in inter-
leaved PWM mode that results in minimal VCORE ripple
and best transient performance. While in light load mode,
indicated by either PSI going low or DPRSLP going high,
only Phase 1 of ADP3210 is in operation to maximize
power conversion efficiency.
In addition to the change of phase number, the ADP3210
dynamically changes operation modes. In multiphase operation,
the ADP3210 runs in PWM mode, with switching frequency
controlled by the master clock. In single-phase mode based on
PSI signal, the ADP3210 switches to RPM mode, where the
switching frequency is no longer controlled by the master clock,
but by the ripple voltage appearing on the COMP pin. The
PWM1 pin is set to high each time the COMP pin voltage rises
to a limit determined by the VID voltage and programmed
by the external resistor connected from Pin RPM to ground. In
single-phase mode based on the DPRSLP signal, the ADP3210
runs in RPM mode, with the synchronous rectifier (low-side)
MOSFETs of Phase 1 being controlled by the DCM pin to
prevent any reverse inductor current. Thus, the switch
frequency varies with the load current, resulting in maximum
power conversion efficiency in deeper sleep mode of CPU
operation. In addition, during any VID transient, system
transient (entry/exit of deeper sleep), or current limit, the
ADP3210 goes into full phase mode, regardless of DPRSLP and
PSI signals, eliminating current stress to Phase 1.
Table 4 summarizes how the ADP3210 dynamically changes
phase number and operation modes based on system signals
and operating conditions.
Rev. 0.3 | Page 14 of 38