ADP3210 Datasheet, PDF (18/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
VOLTAGE CONTROL MODE
A high gain bandwidth error amplifier is used for the voltage-
mode control loop. The noninverting input voltage is set via the
7-bit VID DAC. The VID codes are listed in Table 5. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
pin has a resistance of approximately 100Ω. When VCC ramps
above the upper UVLO threshold and EN is asserted high, the
ADP3210 enables internal bias and starts a reset cycle that lasts
about 50 μs to 60 μs. Next, when initial reset is over, the chip
detects the number of phases set by the user, and gives a go
signal to start soft start. The ADP3210 reads the VID codes
provided by the CPU on VID0 to VID6 input pins after
CLKEN# is asserted low.
The negative input, FB, is tied to the output sense location
through a resistor, RB, for sensing and controlling the output
voltage at the remote sense point. The main loop compensation
is incorporated in the feedback network connected between FB
and COMP.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output that
can be pulled up through an external resistor to a voltage rail
that is not necessarily the same VCC voltage rail of the
controller. Logic high level indicates that the output voltage is
within the voltage limits defined by a window around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of that window.
Following the IMVP-6.5 specification, PWRGD window is
defined as −300 mV below and +200 mV above the actual VID
DAC output voltage. For any DAC voltage below 300 mV, only
the upper limit of the PWRGD window is monitored. To
prevent false alarm, the power-good circuit is masked during
various system transitions, including any VID change and
entrance/exit out of deeper sleep. The duration of the PWRGD
mask time is set by an internal clock to approximately 100 μs.
During a VID change, the PWRGD signal is masked to prevent
false PWRGD glitches. The PWRGD is masked for
approximately 100 μs after a VID change.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set
internally. During start up, the ADP3210 steps sequentially
through each VID code until it reaches the boot voltage. The
whole power-up sequence, including soft start, is illustrated in
Figure 22.
After EN is asserted high, the soft start sequence starts. The
core voltage ramps up linearly to the boot voltage. The
ADP3210 regulates at the boot voltage for 100 μs. After the boot
time is completed, CLKEN# is asserted low. After CLKEN# is
asserted low for 9ms, PWRGD is asserted high.
In VCC UVLO or in shutdown, a small MOSFET turns on
connecting the CSREF to GND. The MOSFET on the CSREF
Figure 22. Power-Up Sequence
SOFT TRANSIENT
The IMVP-6.5 specification requires the CPU to step through the
VID codes in 12.5mV steps when transitioning from one VID code
to another. This reducing the inrush current and helps decrease
the acoustic noise generated by the MLCC input capacitors and
inductors.
The ADP3210 also offers soft transient control for large VID
step changes. When the VID is changed, the ADP3210 changes
the output voltage 1 LSB every 1 μs. The output voltage slew
rate is controlled to 12.5 mV/μs.
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION
The ADP3210 compares the differential output of a current-
sense amplifier to a programmable current-limit setpoint to
provide current-limiting function. The current limit set point is
set with a resistor connected from ILIM pin to CSCOMP pin.
This is the Rlim resistor. During normal operation, the voltage
on the ILIM pin is equal to the CSREF pin. The voltage across
Rlim is equal to the voltage across the current sense amplifier
(from CSREF pin to CSCOMP pin). This voltage is
proportional to output current. The current through Rlim is
proportional to the output inductor current. The current
through Rlim is compared with an internal reference current.
When the Rlim current goes above the internal reference current,
the ADP3210 goes into current limit. The current limit circuit is
shown in Figure 29.
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