ADP3210 Datasheet, PDF (30/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
where:
AR is the internal ramp amplifier gain.
CR is the internal ramp capacitor value.
RR is an external resistor on the RAMPADJ pin to set the
internal ramp magnitude.
Because RR = 280 kΩ, the following resistance sets up 300 kHz
switching frequency in RPM operation.
R _RPM
= ^{2 × 280 kΩ} × ^{0.5 × (1 − 0.061) ×1.150}
1.150 V + 1.0 V 462 k Ω × 5 pF × 300 kHz
− 500 Ω = 202 kΩ
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, we need to find the resistor
value for R_LIM. The current-limit threshold for the ADP3210 is
set when the current in R_LIM is equal to the internal reference
current of 20 μA. The current in R_LIM is equal to the inductor
current times R_O. R_LIM can be found using the following
equation:
R_LIM
=
I_LIM × R_O
20μA
(25)
where:
R_LIM is the current limit resistor. R_LIM is connected from the
ILIM pin to CSCOMP.
R_O is the output load line resistance.
I_LIM is the current limit set point. This is the peak inductor
current that will trip current limit.
In this example, if choosing 55 A for ILIM, RLIM is 5.775 kΩ,
which is close to a standard 1% resistance of 5.76 kΩ.
The per-phase current limit described earlier has its limit
determined by the following:
I _PHLIM
≅
V_COMP(MAX) − V_R − V_BIAS
A_D × R_DS(MAX)
+
I_R
2
(26)
For the ADP3210, the maximum COMP voltage (VCOMP(MAX)) is
3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the
current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V,
and a RDS(MAX) of 3.8 mΩ (low-side on-resistance at 150°C)
results in a per-phase limit of 85 A. Although this number
seems high, this current level can only be reached with a
absolute short at the output and the current-limit latch-off
function shutting down the regulator before overheating occurs.
This limit can be adjusted by changing the ramp voltage VR.
However, users should not set the per-phase limit lower than
the average per-phase current (ILIM/n).
There is also a per-phase initial duty-cycle limit at maximum
input voltage:
D _LIM
= D _MIN
× ^VCOMP(MAX)
V_R
− V_BIAS
(27)
For this example, the duty-cycle limit at maximum input
voltage is found to be 0.25 when D is 0.061.
OUTPUT CURRENT MONITOR
The ADP3210 has output current monitor. The IMON pin
sources a current proportional to the total inductor current. A
resistor, R_MON, from IMON to FBRTN sets the gain of the
output current monitor. A 0.1 μF is placed in parallel with R_MON
to filter the inductor current ripple and high frequency load
transients. Since the IMON pin is connected directly to the
CPU, it is clamped to prevent it from going above 1.15V.
The IMON pin current is equal to the R_LIMtimes a fixed gain of
10. R_MON can be found using the following equation:
R_MON
=
1.15V × R_LIM
10× R_O × I_FS
(28)
where:
R_MON is the current monitor resistor. R_MON is connected from
IMON pin to FBRTN.
R_LIM is the current limit resistor.
R_O is the output load line resistance.
I_FS is the output current when the voltage on IMON is at full
scale.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3210 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(RO). With the resistive output impedance, the output voltage
droops in proportion with the load current at any load current
slew rate. This ensures the optimal positioning and minimizes
the output decoupling.
With the multimode feedback structure of the ADP3210, users
need to set the feedback compensation to make the converter
output impedance work in parallel with the output decoupling.
Several poles and zeros are created by the output inductor and
decoupling capacitors (output filter) that need to be
compensated for.
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equation 29 to
Equation 35 is intended to yield an optimal starting point for
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