ADP3210 Datasheet, PDF (29/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

For example, using an IRF7821 device as the main MOSFET
(four in total; that is, nMF = 4), with about CISS = 1010 pF (max)
and RDS(MF) = 18 mΩ (max at TJ = 120°C) and an IR7832 device
as the synchronous MOSFET (four in total; that is, nSF = 4),
RDS(SF) = 6.7 mΩ (max at TJ = 120°C). Solving for the power
dissipation per MOSFET at IO = 32 A and IR = 10.7 A yields
420 mW for each synchronous MOSFET and 410 mW for each
main MOSFET.
One last consideration is the power dissipation in the driver for
each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
( ) P_DRV
=
⎡
⎢⎣
f_SW
2 ×n
×
n_MF
× Q_GMF
+ n_SF
× Q_GSF
+
I_CC
⎤
⎥⎦
×
V_CC
(20)
where:
QGMF is the total gate charge for each main MOSFET.
QGSF is the total gate charge for each synchronous MOSFET.
Also shown is the standby dissipation (ICC × VCC) of the driver.
For the ADP3419, the maximum dissipation should be less than
300 mW, considering its thermal impedance is 220°C/W and
the maximum temperature increase is 50°C. For this example,
with ICC = 2 mA, QGMF = 14 nC and QGSF = 51 nC, there is 120
mW dissipation in each driver, which is below the 300 mW
dissipation limit. See the ADP3419 data sheet for more details.
ADP3210
V_R
=
A_R × (1 − D) ×V_VID
R_R × C_R × f_SW
(22)
V_R
=
0.5 × (1 − 0.061) ×1.150 V
462 kΩ × 5 pF × 280 kHz
=
0.83 V
The size of the internal ramp can be made larger or smaller. If it
is made larger, then stability and transient response improves,
but thermal balance degrades. Likewise, if the ramp is made
smaller, then thermal balance improves at the sacrifice of
transient response and stability. The factor of three in the
denominator of Equation 21 sets a minimum ramp size that
gives an optimal balance for good stability, transient response,
and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input:
V_RT
=
V_R
⎜⎜⎝⎛¹
−
n
2 × (1
× f _SW
−
×
n
C
×
X
D
×
)
R_O
⎟⎟⎠⎞
(23)
For this example, the overall ramp signal is found to be 1.5 V.
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. Use this equation to determine a starting value
R_R
=
3×
A_R × L
A_D × R_DS
× C_R
(21)
R_R
=
0.5 × 360 nH
3× 5 × 5.2 mΩ × 5 pF
=
462 kΩ
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low-side MOSFET ON-resistance,
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 22). For stability and noise
immunity, keep this ramp size larger than 0.5 V. Taking this into
consideration, the value of RR is selected as 280 kΩ.
The internal ramp voltage magnitude can be calculated using:
SETTING THE SWITCHING FREQUENCY FOR RPM
MODE OPERATION OF PHASE 1
During the RPM mode operation of Phase 1, the ADP3210 runs
in pseudo constant frequency, given that the load current is
high enough for continuous current mode. While in
discontinuous current mode, the switching frequency is
reduced with the load current in a linear manner. When
considering power conversion efficiency in light load, lower
switching frequency is usually preferred for RPM mode.
However, the VCORE ripple specification in the IMVP-6 sets the
limitation for lowest switching frequency. Therefore, depending
on the inductor and output capacitors, the switching frequency
in RPM mode can be equal, larger, or smaller than its
counterpart in PWM mode.
A resistor from RPM to GND sets the pseudo constant
frequency as following:
R _RPM
= ^{2 × RT} ×
V_VID + 1.0 V
A_R × (1 − D) ×V_VID
R_R × C_R × f _SW
− 0.5kΩ
(24)
Rev. 0.3 | Page 29 of 38