ADP3210 Datasheet, PDF (20/38 Pages) ON Semiconductor – 7-Bit Programmable Multiphase Mobile CPU Synchronous

ADP3210
Occasionally, overvoltage crowbar protection results in negative
VCORE voltage, because turn-on of all low-side MOSFETs leads
to very large reverse inductor current. To prevent damage of the
CPU by negative voltage, ADP3210 keeps its RVP monitoring
function alive even after OVP latch-off. During OVP latch-off,
if the CSREF pin voltage drops below −300mV, then all low-side
MOSFETs are turned off by setting both DCM and OD low.
DCM and OD pins are set high again when CSREF voltage
recovers above −100 mV.
OUTPUT ENABLE AND UVLO
The VCC supply voltage to the controller must be higher than
the UVLO upper threshold, and the EN pin must be higher
than its logic threshold so the ADP3210 can begin switching. If
the VCC voltage is less than the UVLO threshold, or the EN pin
is logic low, then the ADP3210 is in shutdown. In shutdown, the
controller holds the PWM outputs at ground, shorts the SS pin
and PGDELAY pin capacitors to ground, and drives DCM and
OD pins low.
Proper power supply sequencing during start-up and shutdown
of the ADP3210 must be adhered to. All input pins must be at
ground prior to applying or removing VCC. All output pins
should be left in high impedance state while VCC is off.
OUTPUT CURRENT MONITOR
The ADP3210 has an output current monitor. The IMON pin
sources a current proportional to the inductor current. A
resistor from IMON pin to FBRTN sets the gain. A 0.1 μF is
added in parallel with RMON to filter the inductor ripple. The
IMON pin is clamped to prevent it from going above 1.15V
THERMAL THROTTLING CONTROL
The ADP3210 includes a thermal monitoring circuit to detect if
the temperature of the variable resistor (VR) has exceeded a
user-defined thermal throttling threshold. The thermal
monitoring circuit requires an external resistor divider
connected between the VCC pin and GND. The divider consists
of an NTC thermistor and a resistor. To generate a voltage that
is proportional to temperature, the midpoint of the divider is
connected to the TTSN pin. Whenever the temperature trips
the set alarm threshold, an internal comparator circuit
compares the TTSN voltage to a half VCC threshold and
outputs a logic level signal at the VRTT output. The VRTT
output is designed to drive an external transistor that, in turn,
provides the high current, open drain VRTT signal that is
required by the IMVP-6.5 specification. When the temperature
is around the set alarm point, the internal VRTT comparator
has a hysteresis of about 100 mV to prevent high frequency
oscillation of VRTT.
Rev. 0.3 | Page 20 of 38