AR0134CS_16 Datasheet, PDF (30/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Power-On Reset and Standby Timing
Power-Up Sequence
The recommended power-up sequence for the AR0134 is shown in Figure 19. The avail-
able power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the
separation specified below.
1. Turn on VDD_PLL power supply.
2. After 0–10s, turn on VAA and VAA_PIX power supply.
3. After 0–10s, turn on VDD_IO power supply.
4. After the last power supply is stable, enable EXTCLK.
5. If RESET_BAR is in a LOW state, hold RESET_BAR LOW for at least 1ms.
If RESET_BAR is in a HIGH state, assert RESET_BAR for at least 1ms.
6. Wait 160000 EXTCLKs (for internal initialization into software standby).
7. Configure PLL, output, and image settings to desired values.
8. Wait 1ms for the PLL to lock.
9. Set streaming mode (R0x301a[2] = 1).
Figure 19: Power Up
VDD_PLL (2.8)
VAA_PIX
VAA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_SLVS (0.4)
EXTCLK
RESET_BAR
t0
t1
t2
t3
tx
t4
Hard Reset
t5
Internal
Initialization
Software
Standby
t6
PLL Lock
Streaming
Table 18: Power-Up Sequence
Definition
VDD_PLL to VAA/VAA_PIX
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
VDD to VDD_SLVS
Xtal settle time
Hard Reset
Internal Initialization
PLL Lock Time
Symbol
t0
t1
t2
t3
tx
t4
t5
t6
Minimum
0
0
0
0
–
1²
160000
1
Typical
10
10
10
10
30¹
–
–
–
Maximum
–
–
–
–
–
–
–
–
Unit
s
s
s
s
ms
ms
EXTCLKs
ms
Notes:
1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
AR0134CS/D Rev. 8, Pub. 1/16 EN
30
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