AR0134CS_16 Datasheet, PDF (22/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Electrical Specifications
I/O Timing
By default, the AR0134 launches pixel data, FV and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV and LV using the rising edge of
PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028. See Figure 15
and Table 6 for I/O timing (AC) characteristics.
Figure 15: I/O Timing Diagram
EXTCLK
tEXTCLK
tR
tF
90%
10%
tRP
tFP
90%
10%
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
tPD
tPLH
tPFH
Pxl _0
Pxl _1
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
Pxl _2
Table 6:
I/O Timing Characteristics, Parallel Output (1.8V VDD_IO)¹
Symbol Definition
Condition
Min
f_EXTCLK Input clock frequency
6
t_EXTCLK Input clock period
20
t_R
Input clock rise time
PLL enabled
t_F
Input clock fall time
PLL enabled
t_jJITTER Input clock jitter
t_cp EXTCLK to PIXCLK propagation Nominal voltages, PLL disabled,
5.7
delay
PIXCLK slew rate = 4
t_RP PIXCLK rise time
PCLK slew rate = 6
1.3
t_FP PIXCLK fall time
PCLK slew rate = 6
1.3
PIXCLK duty cycle
40
f_{PIXCLK PIXCLK frequency}
PIXCLK slew rate = 6,
Data slew rate = 7
6
t_PD
PIXCLK to data valid
PIXCLK slew rate = 6,
Data slew rate = 7
-2.5
t_{PFH PIXCLK to FV HIGH}
PIXCLK slew rate = 6,
Data slew rate = 7
-2.5
t_{PLH PIXCLK to LV HIGH}
PIXCLK slew rate = 6,
Data slew rate = 7
-3
t_PFL
PIXCLK to FV LOW
PIXCLK slew rate = 6,
Data slew rate = 7
-2.5
t_PLL
PIXCLK to LV LOW
PIXCLK slew rate = 6,
Data slew rate = 7
-3
CIN Input pin capacitance
Pxl _n
tPFL
tPLL
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
Typ Max Unit
50
MHz
166
ns
3
ns
3
ns
600
ns
14.3
ns
4.0
ns
3.9
ns
50
60
%
74.25 MHz
2
ns
2
ns
1.5
ns
2
ns
1.5
ns
2.5
pf
AR0134CS/D Rev. 8, Pub. 1/16 EN
22
©Semiconductor Components Industries, LLC,2016.