AR0134CS_16 Datasheet, PDF (28/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Electrical Specifications
Figure 16: Differential Output Voltage for Clock or Data Pairs
VDIFFmin
VDIFFmax
0V Diff)
Output Signal is 'Cp - Cn' or 'Dp - Dn'
Table 17:
Rise and Fall Times
Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz
Parameter
Symbol
Min
Typ
Max
Unit
Data Rate
Max setup time from transmitter
Max hold time from transmitter
Rise time (20% - 80%)
Fall time (20% - 80%)
Clock duty
Bitrate Period
Eye Width
Data Total jitter (pk pk)@1e-9
Clock Period Jitter (RMS)
Clock cycle to cycle jitter (RMS)
Clock to Data Skew
PHY-to-PHY Skew
Mean differential skew
1/UI
TxPRE
TxPost
RISE
FALL
PLL_DUTY
t_pw
t_eye
t_totaljit
t_ckjit
t_cyjit
t_chskew
t_|PHYskew|
t_DIFFSKEW
280
0.3
0.3
–
150ps
45
1.43
0.3
-0.1
–100
–
700
–
–
–
–
0.25UI
–
0.25 UI
–
50
55
3.57
0.2
50
100
0.1
2.1
100
Mb/s
UI¹
UI
%
ns¹
UI^{1, 2}
UI^{1, 2}
ps²
ps²
UI^{1, 2}
UI^{1, 5}
ps⁶
Notes:
1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from 0V crossing point.
3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY
between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point.
AR0134CS/D Rev. 8, Pub. 1/16 EN
28
©Semiconductor Components Industries, LLC,2016.