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AR0134CS_16 Datasheet, PDF (21/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Electrical Specifications
Table 5:
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard-Mode
Fast-Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
Set-up time for STOP condition
tSU;STO
4.0
-
0.6
-
S
Bus free time between a STOP and START
tBUF
4.7
-
1.3
-
S
condition
Capacitive load for each bus line
Cb
-
400
-
400
pF
Serial interface input pin capacitance
CIN_SI
-
3.3
-
3.3
pF
SDATA max load capacitance
CLOAD_SD
-
30
-
30
pF
SDATA pull-up resistor
RSD
1.5
4.7
1.5
4.7
K
Notes:
1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
AR0134CS/D Rev. 8, Pub. 1/16 EN
21
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