AR0134CS_16 Datasheet, PDF (16/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Message Byte
Acknowledge Bit
No-Acknowledge Bit
Typical Sequence
An alternate slave address can also be programmed through R0x31FC.
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data.
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
ScLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when ScLK is LOW
and must be stable while ScLK is HIGH.
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the ScLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-
cates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowl-
edge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
the WRITE should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a WRITE request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, eight bits at a time. The master generates an acknowledge
bit after each 8-bit transfer. The slave’s internal register address is automatically incre-
mented after every 8 bits are transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
AR0134CS/D Rev. 8, Pub. 1/16 EN
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